1/* |
2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * |
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright --- 75 unchanged lines hidden (view full) --- 97 return 0; 98 } 99 100 }; 101 102 AtomicCPUPort icachePort; 103 AtomicCPUPort dcachePort; 104 |
105 bool fastmem; |
106 Request ifetch_req; 107 Request data_read_req; 108 Request data_write_req; 109 110 bool dcache_access; 111 Tick dcache_latency; 112 113 Range<Addr> physMemAddr; 114 115 protected: 116 117 /** Return a reference to the data port. */ 118 virtual CpuPort &getDataPort() { return dcachePort; } 119 120 /** Return a reference to the instruction port. */ 121 virtual CpuPort &getInstPort() { return icachePort; } 122 123 public: 124 |
125 virtual void serialize(std::ostream &os); 126 virtual void unserialize(Checkpoint *cp, const std::string §ion); 127 virtual void resume(); 128 129 void switchOut(); 130 void takeOverFrom(BaseCPU *oldCPU); 131 132 virtual void activateContext(ThreadID thread_num, int delay); --- 15 unchanged lines hidden --- |