1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 50 unchanged lines hidden (view full) --- 59 const int width; 60 bool locked; 61 const bool simulate_data_stalls; 62 const bool simulate_inst_stalls; 63 64 // main simulation loop (one cycle) 65 void tick(); 66 |
67 /** 68 * An AtomicCPUPort overrides the default behaviour of the 69 * recvAtomic and ignores the packet instead of panicking. 70 */ 71 class AtomicCPUPort : public CpuPort |
72 { |
73 |
74 public: 75 |
76 AtomicCPUPort(const std::string &_name, BaseCPU* _cpu) 77 : CpuPort(_name, _cpu) |
78 { } 79 |
80 protected: 81 |
82 virtual Tick recvAtomic(PacketPtr pkt) 83 { 84 // Snooping a coherence request, just return 85 return 0; 86 } |
87 |
88 }; |
89 |
90 AtomicCPUPort icachePort; 91 AtomicCPUPort dcachePort; |
92 93 CpuPort physmemPort; 94 bool hasPhysMemPort; 95 Request ifetch_req; 96 Request data_read_req; 97 Request data_write_req; 98 99 bool dcache_access; --- 31 unchanged lines hidden --- |