2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#ifndef __CPU_SIMPLE_ATOMIC_HH__ 32#define __CPU_SIMPLE_ATOMIC_HH__ 33 34#include "cpu/simple/base.hh" 35#include "params/AtomicSimpleCPU.hh" 36 37class AtomicSimpleCPU : public BaseSimpleCPU 38{ 39 public: 40 41 AtomicSimpleCPU(AtomicSimpleCPUParams *params); 42 virtual ~AtomicSimpleCPU(); 43 44 virtual void init(); 45 46 private: 47 48 struct TickEvent : public Event 49 { 50 AtomicSimpleCPU *cpu; 51 52 TickEvent(AtomicSimpleCPU *c); 53 void process(); 54 const char *description() const; 55 }; 56 57 TickEvent tickEvent; 58 59 const int width; 60 bool locked; 61 const bool simulate_data_stalls; 62 const bool simulate_inst_stalls; 63 64 // main simulation loop (one cycle) 65 void tick(); 66 67 /** 68 * An AtomicCPUPort overrides the default behaviour of the 69 * recvAtomic and ignores the packet instead of panicking. 70 */ 71 class AtomicCPUPort : public CpuPort 72 { 73 74 public: 75 76 AtomicCPUPort(const std::string &_name, BaseCPU* _cpu) 77 : CpuPort(_name, _cpu) 78 { } 79 80 protected: 81 82 virtual Tick recvAtomic(PacketPtr pkt) 83 { 84 // Snooping a coherence request, just return 85 return 0; 86 } 87 88 }; 89 90 AtomicCPUPort icachePort; 91 AtomicCPUPort dcachePort; 92
| 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 */ 42 43#ifndef __CPU_SIMPLE_ATOMIC_HH__ 44#define __CPU_SIMPLE_ATOMIC_HH__ 45 46#include "cpu/simple/base.hh" 47#include "params/AtomicSimpleCPU.hh" 48 49class AtomicSimpleCPU : public BaseSimpleCPU 50{ 51 public: 52 53 AtomicSimpleCPU(AtomicSimpleCPUParams *params); 54 virtual ~AtomicSimpleCPU(); 55 56 virtual void init(); 57 58 private: 59 60 struct TickEvent : public Event 61 { 62 AtomicSimpleCPU *cpu; 63 64 TickEvent(AtomicSimpleCPU *c); 65 void process(); 66 const char *description() const; 67 }; 68 69 TickEvent tickEvent; 70 71 const int width; 72 bool locked; 73 const bool simulate_data_stalls; 74 const bool simulate_inst_stalls; 75 76 // main simulation loop (one cycle) 77 void tick(); 78 79 /** 80 * An AtomicCPUPort overrides the default behaviour of the 81 * recvAtomic and ignores the packet instead of panicking. 82 */ 83 class AtomicCPUPort : public CpuPort 84 { 85 86 public: 87 88 AtomicCPUPort(const std::string &_name, BaseCPU* _cpu) 89 : CpuPort(_name, _cpu) 90 { } 91 92 protected: 93 94 virtual Tick recvAtomic(PacketPtr pkt) 95 { 96 // Snooping a coherence request, just return 97 return 0; 98 } 99 100 }; 101 102 AtomicCPUPort icachePort; 103 AtomicCPUPort dcachePort; 104
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121 virtual void serialize(std::ostream &os); 122 virtual void unserialize(Checkpoint *cp, const std::string §ion); 123 virtual void resume(); 124 125 void switchOut(); 126 void takeOverFrom(BaseCPU *oldCPU); 127 128 virtual void activateContext(ThreadID thread_num, int delay); 129 virtual void suspendContext(ThreadID thread_num); 130 131 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 132 133 Fault writeMem(uint8_t *data, unsigned size, 134 Addr addr, unsigned flags, uint64_t *res); 135 136 /** 137 * Print state of address in memory system via PrintReq (for 138 * debugging). 139 */ 140 void printAddr(Addr a); 141}; 142 143#endif // __CPU_SIMPLE_ATOMIC_HH__
| 125 virtual void serialize(std::ostream &os); 126 virtual void unserialize(Checkpoint *cp, const std::string §ion); 127 virtual void resume(); 128 129 void switchOut(); 130 void takeOverFrom(BaseCPU *oldCPU); 131 132 virtual void activateContext(ThreadID thread_num, int delay); 133 virtual void suspendContext(ThreadID thread_num); 134 135 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 136 137 Fault writeMem(uint8_t *data, unsigned size, 138 Addr addr, unsigned flags, uint64_t *res); 139 140 /** 141 * Print state of address in memory system via PrintReq (for 142 * debugging). 143 */ 144 void printAddr(Addr a); 145}; 146 147#endif // __CPU_SIMPLE_ATOMIC_HH__
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