1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_ATOMIC_HH__
32#define __CPU_SIMPLE_ATOMIC_HH__
33
34#include "cpu/simple/base.hh"
35#include "params/AtomicSimpleCPU.hh"
36
37class AtomicSimpleCPU : public BaseSimpleCPU
38{
39 public:
40
41 AtomicSimpleCPU(AtomicSimpleCPUParams *params);
42 virtual ~AtomicSimpleCPU();
43
44 virtual void init();
45
46 private:
47
48 struct TickEvent : public Event
49 {
50 AtomicSimpleCPU *cpu;
51
52 TickEvent(AtomicSimpleCPU *c);
53 void process();
54 const char *description() const;
55 };
56
57 TickEvent tickEvent;
58
59 const int width;
60 bool locked;
61 const bool simulate_data_stalls;
62 const bool simulate_inst_stalls;
63
64 // main simulation loop (one cycle)
65 void tick();
66
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_ATOMIC_HH__
32#define __CPU_SIMPLE_ATOMIC_HH__
33
34#include "cpu/simple/base.hh"
35#include "params/AtomicSimpleCPU.hh"
36
37class AtomicSimpleCPU : public BaseSimpleCPU
38{
39 public:
40
41 AtomicSimpleCPU(AtomicSimpleCPUParams *params);
42 virtual ~AtomicSimpleCPU();
43
44 virtual void init();
45
46 private:
47
48 struct TickEvent : public Event
49 {
50 AtomicSimpleCPU *cpu;
51
52 TickEvent(AtomicSimpleCPU *c);
53 void process();
54 const char *description() const;
55 };
56
57 TickEvent tickEvent;
58
59 const int width;
60 bool locked;
61 const bool simulate_data_stalls;
62 const bool simulate_inst_stalls;
63
64 // main simulation loop (one cycle)
65 void tick();
66
|
67 class CpuPort : public Port
| 67 /**
68 * An AtomicCPUPort overrides the default behaviour of the
69 * recvAtomic and ignores the packet instead of panicking.
70 */
71 class AtomicCPUPort : public CpuPort
|
68 {
| 72 {
|
| 73
|
69 public:
70
| 74 public:
75
|
71 CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu)
72 : Port(_name, _cpu), cpu(_cpu)
| 76 AtomicCPUPort(const std::string &_name, BaseCPU* _cpu)
77 : CpuPort(_name, _cpu)
|
73 { }
74
| 78 { }
79
|
75 bool snoopRangeSent;
76
| |
77 protected:
78
| 80 protected:
81
|
79 AtomicSimpleCPU *cpu;
| 82 virtual Tick recvAtomic(PacketPtr pkt)
83 {
84 // Snooping a coherence request, just return
85 return 0;
86 }
|
80
| 87
|
81 virtual bool recvTiming(PacketPtr pkt);
82
83 virtual Tick recvAtomic(PacketPtr pkt);
84
85 virtual void recvFunctional(PacketPtr pkt);
86
87 virtual void recvStatusChange(Status status);
88
89 virtual void recvRetry();
90
91 virtual void getDeviceAddressRanges(AddrRangeList &resp,
92 bool &snoop)
93 { resp.clear(); snoop = true; }
94
| |
95 };
| 88 };
|
96 CpuPort icachePort;
| |
97
| 89
|
98 CpuPort dcachePort;
| 90 AtomicCPUPort icachePort;
91 AtomicCPUPort dcachePort;
|
99
100 CpuPort physmemPort;
101 bool hasPhysMemPort;
102 Request ifetch_req;
103 Request data_read_req;
104 Request data_write_req;
105
106 bool dcache_access;
107 Tick dcache_latency;
108
109 Range<Addr> physMemAddr;
110
111 public:
112
113 virtual Port *getPort(const std::string &if_name, int idx = -1);
114
115 virtual void serialize(std::ostream &os);
116 virtual void unserialize(Checkpoint *cp, const std::string §ion);
117 virtual void resume();
118
119 void switchOut();
120 void takeOverFrom(BaseCPU *oldCPU);
121
122 virtual void activateContext(int thread_num, int delay);
123 virtual void suspendContext(int thread_num);
124
125 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
126
127 Fault writeMem(uint8_t *data, unsigned size,
128 Addr addr, unsigned flags, uint64_t *res);
129
130 /**
131 * Print state of address in memory system via PrintReq (for
132 * debugging).
133 */
134 void printAddr(Addr a);
135};
136
137#endif // __CPU_SIMPLE_ATOMIC_HH__
| 92
93 CpuPort physmemPort;
94 bool hasPhysMemPort;
95 Request ifetch_req;
96 Request data_read_req;
97 Request data_write_req;
98
99 bool dcache_access;
100 Tick dcache_latency;
101
102 Range<Addr> physMemAddr;
103
104 public:
105
106 virtual Port *getPort(const std::string &if_name, int idx = -1);
107
108 virtual void serialize(std::ostream &os);
109 virtual void unserialize(Checkpoint *cp, const std::string §ion);
110 virtual void resume();
111
112 void switchOut();
113 void takeOverFrom(BaseCPU *oldCPU);
114
115 virtual void activateContext(int thread_num, int delay);
116 virtual void suspendContext(int thread_num);
117
118 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
119
120 Fault writeMem(uint8_t *data, unsigned size,
121 Addr addr, unsigned flags, uint64_t *res);
122
123 /**
124 * Print state of address in memory system via PrintReq (for
125 * debugging).
126 */
127 void printAddr(Addr a);
128};
129
130#endif // __CPU_SIMPLE_ATOMIC_HH__
|