atomic.hh (5529:9ae69b9cd7fd) atomic.hh (5890:bdef71accd68)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_ATOMIC_HH__
32#define __CPU_SIMPLE_ATOMIC_HH__
33
34#include "cpu/simple/base.hh"
35#include "params/AtomicSimpleCPU.hh"
36
37class AtomicSimpleCPU : public BaseSimpleCPU
38{
39 public:
40
41 AtomicSimpleCPU(AtomicSimpleCPUParams *params);
42 virtual ~AtomicSimpleCPU();
43
44 virtual void init();
45
46 private:
47
48 struct TickEvent : public Event
49 {
50 AtomicSimpleCPU *cpu;
51
52 TickEvent(AtomicSimpleCPU *c);
53 void process();
54 const char *description() const;
55 };
56
57 TickEvent tickEvent;
58
59 const int width;
60 const bool simulate_data_stalls;
61 const bool simulate_inst_stalls;
62
63 // main simulation loop (one cycle)
64 void tick();
65
66 class CpuPort : public Port
67 {
68 public:
69
70 CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu)
71 : Port(_name, _cpu), cpu(_cpu)
72 { }
73
74 bool snoopRangeSent;
75
76 protected:
77
78 AtomicSimpleCPU *cpu;
79
80 virtual bool recvTiming(PacketPtr pkt);
81
82 virtual Tick recvAtomic(PacketPtr pkt);
83
84 virtual void recvFunctional(PacketPtr pkt);
85
86 virtual void recvStatusChange(Status status);
87
88 virtual void recvRetry();
89
90 virtual void getDeviceAddressRanges(AddrRangeList &resp,
91 bool &snoop)
92 { resp.clear(); snoop = true; }
93
94 };
95 CpuPort icachePort;
96
97 class DcachePort : public CpuPort
98 {
99 public:
100 DcachePort(const std::string &_name, AtomicSimpleCPU *_cpu)
101 : CpuPort(_name, _cpu)
102 { }
103
104 virtual void setPeer(Port *port);
105 };
106 DcachePort dcachePort;
107
108 CpuPort physmemPort;
109 bool hasPhysMemPort;
110 Request ifetch_req;
111 Request data_read_req;
112 Request data_write_req;
113
114 bool dcache_access;
115 Tick dcache_latency;
116
117 Range<Addr> physMemAddr;
118
119 public:
120
121 virtual Port *getPort(const std::string &if_name, int idx = -1);
122
123 virtual void serialize(std::ostream &os);
124 virtual void unserialize(Checkpoint *cp, const std::string &section);
125 virtual void resume();
126
127 void switchOut();
128 void takeOverFrom(BaseCPU *oldCPU);
129
130 virtual void activateContext(int thread_num, int delay);
131 virtual void suspendContext(int thread_num);
132
133 template <class T>
134 Fault read(Addr addr, T &data, unsigned flags);
135
136 template <class T>
137 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
138
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_ATOMIC_HH__
32#define __CPU_SIMPLE_ATOMIC_HH__
33
34#include "cpu/simple/base.hh"
35#include "params/AtomicSimpleCPU.hh"
36
37class AtomicSimpleCPU : public BaseSimpleCPU
38{
39 public:
40
41 AtomicSimpleCPU(AtomicSimpleCPUParams *params);
42 virtual ~AtomicSimpleCPU();
43
44 virtual void init();
45
46 private:
47
48 struct TickEvent : public Event
49 {
50 AtomicSimpleCPU *cpu;
51
52 TickEvent(AtomicSimpleCPU *c);
53 void process();
54 const char *description() const;
55 };
56
57 TickEvent tickEvent;
58
59 const int width;
60 const bool simulate_data_stalls;
61 const bool simulate_inst_stalls;
62
63 // main simulation loop (one cycle)
64 void tick();
65
66 class CpuPort : public Port
67 {
68 public:
69
70 CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu)
71 : Port(_name, _cpu), cpu(_cpu)
72 { }
73
74 bool snoopRangeSent;
75
76 protected:
77
78 AtomicSimpleCPU *cpu;
79
80 virtual bool recvTiming(PacketPtr pkt);
81
82 virtual Tick recvAtomic(PacketPtr pkt);
83
84 virtual void recvFunctional(PacketPtr pkt);
85
86 virtual void recvStatusChange(Status status);
87
88 virtual void recvRetry();
89
90 virtual void getDeviceAddressRanges(AddrRangeList &resp,
91 bool &snoop)
92 { resp.clear(); snoop = true; }
93
94 };
95 CpuPort icachePort;
96
97 class DcachePort : public CpuPort
98 {
99 public:
100 DcachePort(const std::string &_name, AtomicSimpleCPU *_cpu)
101 : CpuPort(_name, _cpu)
102 { }
103
104 virtual void setPeer(Port *port);
105 };
106 DcachePort dcachePort;
107
108 CpuPort physmemPort;
109 bool hasPhysMemPort;
110 Request ifetch_req;
111 Request data_read_req;
112 Request data_write_req;
113
114 bool dcache_access;
115 Tick dcache_latency;
116
117 Range<Addr> physMemAddr;
118
119 public:
120
121 virtual Port *getPort(const std::string &if_name, int idx = -1);
122
123 virtual void serialize(std::ostream &os);
124 virtual void unserialize(Checkpoint *cp, const std::string &section);
125 virtual void resume();
126
127 void switchOut();
128 void takeOverFrom(BaseCPU *oldCPU);
129
130 virtual void activateContext(int thread_num, int delay);
131 virtual void suspendContext(int thread_num);
132
133 template <class T>
134 Fault read(Addr addr, T &data, unsigned flags);
135
136 template <class T>
137 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
138
139 Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
140 int size, unsigned flags);
141 Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
142 int size, unsigned flags);
143
144 /**
145 * Print state of address in memory system via PrintReq (for
146 * debugging).
147 */
148 void printAddr(Addr a);
149};
150
151#endif // __CPU_SIMPLE_ATOMIC_HH__
139 /**
140 * Print state of address in memory system via PrintReq (for
141 * debugging).
142 */
143 void printAddr(Addr a);
144};
145
146#endif // __CPU_SIMPLE_ATOMIC_HH__