1/* 2 * Copyright (c) 2012-2013,2015 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 */ 42 43#ifndef __CPU_SIMPLE_ATOMIC_HH__ 44#define __CPU_SIMPLE_ATOMIC_HH__ 45 46#include "cpu/simple/base.hh" 47#include "cpu/simple/exec_context.hh" 48#include "mem/request.hh" 49#include "params/AtomicSimpleCPU.hh" 50#include "sim/probe/probe.hh" 51 52class AtomicSimpleCPU : public BaseSimpleCPU 53{ 54 public: 55 56 AtomicSimpleCPU(AtomicSimpleCPUParams *params); 57 virtual ~AtomicSimpleCPU(); 58 59 void init() override; 60 61 private: 62
| 1/* 2 * Copyright (c) 2012-2013,2015 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 */ 42 43#ifndef __CPU_SIMPLE_ATOMIC_HH__ 44#define __CPU_SIMPLE_ATOMIC_HH__ 45 46#include "cpu/simple/base.hh" 47#include "cpu/simple/exec_context.hh" 48#include "mem/request.hh" 49#include "params/AtomicSimpleCPU.hh" 50#include "sim/probe/probe.hh" 51 52class AtomicSimpleCPU : public BaseSimpleCPU 53{ 54 public: 55 56 AtomicSimpleCPU(AtomicSimpleCPUParams *params); 57 virtual ~AtomicSimpleCPU(); 58 59 void init() override; 60 61 private: 62
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74 const int width; 75 bool locked; 76 const bool simulate_data_stalls; 77 const bool simulate_inst_stalls; 78 79 // main simulation loop (one cycle) 80 void tick(); 81 82 /** 83 * Check if a system is in a drained state. 84 * 85 * We need to drain if: 86 * <ul> 87 * <li>We are in the middle of a microcode sequence as some CPUs 88 * (e.g., HW accelerated CPUs) can't be started in the middle 89 * of a gem5 microcode sequence. 90 * 91 * <li>The CPU is in a LLSC region. This shouldn't normally happen 92 * as these are executed atomically within a single tick() 93 * call. The only way this can happen at the moment is if 94 * there is an event in the PC event queue that affects the 95 * CPU state while it is in an LLSC region. 96 * 97 * <li>Stay at PC is true. 98 * </ul> 99 */ 100 bool isDrained() { 101 SimpleExecContext &t_info = *threadInfo[curThread]; 102 103 return t_info.thread->microPC() == 0 && 104 !locked && 105 !t_info.stayAtPC; 106 } 107 108 /** 109 * Try to complete a drain request. 110 * 111 * @returns true if the CPU is drained, false otherwise. 112 */ 113 bool tryCompleteDrain(); 114 115 /** 116 * An AtomicCPUPort overrides the default behaviour of the 117 * recvAtomicSnoop and ignores the packet instead of panicking. It 118 * also provides an implementation for the purely virtual timing 119 * functions and panics on either of these. 120 */ 121 class AtomicCPUPort : public MasterPort 122 { 123 124 public: 125 126 AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu) 127 : MasterPort(_name, _cpu) 128 { } 129 130 protected: 131 132 bool recvTimingResp(PacketPtr pkt) 133 { 134 panic("Atomic CPU doesn't expect recvTimingResp!\n"); 135 return true; 136 } 137 138 void recvReqRetry() 139 { 140 panic("Atomic CPU doesn't expect recvRetry!\n"); 141 } 142 143 }; 144 145 class AtomicCPUDPort : public AtomicCPUPort 146 { 147 148 public: 149 150 AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu) 151 : AtomicCPUPort(_name, _cpu), cpu(_cpu) 152 { 153 cacheBlockMask = ~(cpu->cacheLineSize() - 1); 154 } 155 156 bool isSnooping() const { return true; } 157 158 Addr cacheBlockMask; 159 protected: 160 BaseSimpleCPU *cpu; 161 162 virtual Tick recvAtomicSnoop(PacketPtr pkt); 163 virtual void recvFunctionalSnoop(PacketPtr pkt); 164 }; 165 166 167 AtomicCPUPort icachePort; 168 AtomicCPUDPort dcachePort; 169 170 bool fastmem; 171 Request ifetch_req; 172 Request data_read_req; 173 Request data_write_req; 174 175 bool dcache_access; 176 Tick dcache_latency; 177 178 /** Probe Points. */ 179 ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit; 180 181 protected: 182 183 /** Return a reference to the data port. */ 184 MasterPort &getDataPort() override { return dcachePort; } 185 186 /** Return a reference to the instruction port. */ 187 MasterPort &getInstPort() override { return icachePort; } 188 189 /** Perform snoop for other cpu-local thread contexts. */ 190 void threadSnoop(PacketPtr pkt, ThreadID sender); 191 192 public: 193 194 DrainState drain() override; 195 void drainResume() override; 196 197 void switchOut() override; 198 void takeOverFrom(BaseCPU *oldCPU) override; 199 200 void verifyMemoryMode() const override; 201 202 void activateContext(ThreadID thread_num) override; 203 void suspendContext(ThreadID thread_num) override; 204 205 Fault readMem(Addr addr, uint8_t *data, unsigned size, 206 Request::Flags flags) override; 207 208 Fault initiateMemRead(Addr addr, unsigned size, 209 Request::Flags flags) override; 210 211 Fault writeMem(uint8_t *data, unsigned size, 212 Addr addr, Request::Flags flags, uint64_t *res) override; 213 214 void regProbePoints() override; 215 216 /** 217 * Print state of address in memory system via PrintReq (for 218 * debugging). 219 */ 220 void printAddr(Addr a); 221}; 222 223#endif // __CPU_SIMPLE_ATOMIC_HH__
| 65 const int width; 66 bool locked; 67 const bool simulate_data_stalls; 68 const bool simulate_inst_stalls; 69 70 // main simulation loop (one cycle) 71 void tick(); 72 73 /** 74 * Check if a system is in a drained state. 75 * 76 * We need to drain if: 77 * <ul> 78 * <li>We are in the middle of a microcode sequence as some CPUs 79 * (e.g., HW accelerated CPUs) can't be started in the middle 80 * of a gem5 microcode sequence. 81 * 82 * <li>The CPU is in a LLSC region. This shouldn't normally happen 83 * as these are executed atomically within a single tick() 84 * call. The only way this can happen at the moment is if 85 * there is an event in the PC event queue that affects the 86 * CPU state while it is in an LLSC region. 87 * 88 * <li>Stay at PC is true. 89 * </ul> 90 */ 91 bool isDrained() { 92 SimpleExecContext &t_info = *threadInfo[curThread]; 93 94 return t_info.thread->microPC() == 0 && 95 !locked && 96 !t_info.stayAtPC; 97 } 98 99 /** 100 * Try to complete a drain request. 101 * 102 * @returns true if the CPU is drained, false otherwise. 103 */ 104 bool tryCompleteDrain(); 105 106 /** 107 * An AtomicCPUPort overrides the default behaviour of the 108 * recvAtomicSnoop and ignores the packet instead of panicking. It 109 * also provides an implementation for the purely virtual timing 110 * functions and panics on either of these. 111 */ 112 class AtomicCPUPort : public MasterPort 113 { 114 115 public: 116 117 AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu) 118 : MasterPort(_name, _cpu) 119 { } 120 121 protected: 122 123 bool recvTimingResp(PacketPtr pkt) 124 { 125 panic("Atomic CPU doesn't expect recvTimingResp!\n"); 126 return true; 127 } 128 129 void recvReqRetry() 130 { 131 panic("Atomic CPU doesn't expect recvRetry!\n"); 132 } 133 134 }; 135 136 class AtomicCPUDPort : public AtomicCPUPort 137 { 138 139 public: 140 141 AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu) 142 : AtomicCPUPort(_name, _cpu), cpu(_cpu) 143 { 144 cacheBlockMask = ~(cpu->cacheLineSize() - 1); 145 } 146 147 bool isSnooping() const { return true; } 148 149 Addr cacheBlockMask; 150 protected: 151 BaseSimpleCPU *cpu; 152 153 virtual Tick recvAtomicSnoop(PacketPtr pkt); 154 virtual void recvFunctionalSnoop(PacketPtr pkt); 155 }; 156 157 158 AtomicCPUPort icachePort; 159 AtomicCPUDPort dcachePort; 160 161 bool fastmem; 162 Request ifetch_req; 163 Request data_read_req; 164 Request data_write_req; 165 166 bool dcache_access; 167 Tick dcache_latency; 168 169 /** Probe Points. */ 170 ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit; 171 172 protected: 173 174 /** Return a reference to the data port. */ 175 MasterPort &getDataPort() override { return dcachePort; } 176 177 /** Return a reference to the instruction port. */ 178 MasterPort &getInstPort() override { return icachePort; } 179 180 /** Perform snoop for other cpu-local thread contexts. */ 181 void threadSnoop(PacketPtr pkt, ThreadID sender); 182 183 public: 184 185 DrainState drain() override; 186 void drainResume() override; 187 188 void switchOut() override; 189 void takeOverFrom(BaseCPU *oldCPU) override; 190 191 void verifyMemoryMode() const override; 192 193 void activateContext(ThreadID thread_num) override; 194 void suspendContext(ThreadID thread_num) override; 195 196 Fault readMem(Addr addr, uint8_t *data, unsigned size, 197 Request::Flags flags) override; 198 199 Fault initiateMemRead(Addr addr, unsigned size, 200 Request::Flags flags) override; 201 202 Fault writeMem(uint8_t *data, unsigned size, 203 Addr addr, Request::Flags flags, uint64_t *res) override; 204 205 void regProbePoints() override; 206 207 /** 208 * Print state of address in memory system via PrintReq (for 209 * debugging). 210 */ 211 void printAddr(Addr a); 212}; 213 214#endif // __CPU_SIMPLE_ATOMIC_HH__
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