atomic.hh (9608:e2b6b86fda03) | atomic.hh (9647:5b6b315472e7) |
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1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 29 unchanged lines hidden (view full) --- 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 */ 42 43#ifndef __CPU_SIMPLE_ATOMIC_HH__ 44#define __CPU_SIMPLE_ATOMIC_HH__ 45 | 1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 29 unchanged lines hidden (view full) --- 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 */ 42 43#ifndef __CPU_SIMPLE_ATOMIC_HH__ 44#define __CPU_SIMPLE_ATOMIC_HH__ 45 |
46#include "base/hashmap.hh" |
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46#include "cpu/simple/base.hh" 47#include "params/AtomicSimpleCPU.hh" 48 | 47#include "cpu/simple/base.hh" 48#include "params/AtomicSimpleCPU.hh" 49 |
50/** 51 * Start and end address of basic block for SimPoint profiling. 52 * This structure is used to look up the hash table of BBVs. 53 * - first: PC of first inst in basic block 54 * - second: PC of last inst in basic block 55 */ 56typedef std::pair<Addr, Addr> BasicBlockRange; 57 58/** Overload hash function for BasicBlockRange type */ 59__hash_namespace_begin 60template <> 61class hash<BasicBlockRange> 62{ 63 public: 64 size_t operator()(const BasicBlockRange &bb) const { 65 return hash<Addr>()(bb.first + bb.second); 66 } 67}; 68__hash_namespace_end 69 70 |
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49class AtomicSimpleCPU : public BaseSimpleCPU 50{ 51 public: 52 53 AtomicSimpleCPU(AtomicSimpleCPUParams *params); 54 virtual ~AtomicSimpleCPU(); 55 56 virtual void init(); --- 99 unchanged lines hidden (view full) --- 156 bool fastmem; 157 Request ifetch_req; 158 Request data_read_req; 159 Request data_write_req; 160 161 bool dcache_access; 162 Tick dcache_latency; 163 | 71class AtomicSimpleCPU : public BaseSimpleCPU 72{ 73 public: 74 75 AtomicSimpleCPU(AtomicSimpleCPUParams *params); 76 virtual ~AtomicSimpleCPU(); 77 78 virtual void init(); --- 99 unchanged lines hidden (view full) --- 178 bool fastmem; 179 Request ifetch_req; 180 Request data_read_req; 181 Request data_write_req; 182 183 bool dcache_access; 184 Tick dcache_latency; 185 |
186 /** 187 * Profile basic blocks for SimPoints. 188 * Called at every macro inst to increment basic block inst counts and 189 * to profile block if end of block. 190 */ 191 void profileSimPoint(); 192 193 /** Data structures for SimPoints BBV generation 194 * @{ 195 */ 196 197 /** Whether SimPoint BBV profiling is enabled */ 198 const bool simpoint; 199 /** SimPoint profiling interval size in instructions */ 200 const uint64_t intervalSize; 201 202 /** Inst count in current basic block */ 203 uint64_t intervalCount; 204 /** Excess inst count from previous interval*/ 205 uint64_t intervalDrift; 206 /** Pointer to SimPoint BBV output stream */ 207 std::ostream *simpointStream; 208 209 /** Basic Block information */ 210 struct BBInfo { 211 /** Unique ID */ 212 uint64_t id; 213 /** Num of static insts in BB */ 214 uint64_t insts; 215 /** Accumulated dynamic inst count executed by BB */ 216 uint64_t count; 217 }; 218 219 /** Hash table containing all previously seen basic blocks */ 220 m5::hash_map<BasicBlockRange, BBInfo> bbMap; 221 /** Currently executing basic block */ 222 BasicBlockRange currentBBV; 223 /** inst count in current basic block */ 224 uint64_t currentBBVInstCount; 225 226 /** @} 227 * End of data structures for SimPoints BBV generation 228 */ 229 |
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164 protected: 165 166 /** Return a reference to the data port. */ 167 virtual MasterPort &getDataPort() { return dcachePort; } 168 169 /** Return a reference to the instruction port. */ 170 virtual MasterPort &getInstPort() { return icachePort; } 171 --- 26 unchanged lines hidden --- | 230 protected: 231 232 /** Return a reference to the data port. */ 233 virtual MasterPort &getDataPort() { return dcachePort; } 234 235 /** Return a reference to the instruction port. */ 236 virtual MasterPort &getInstPort() { return icachePort; } 237 --- 26 unchanged lines hidden --- |