atomic.hh (8922:17f037ad8918) | atomic.hh (8926:570b44fe6e04) |
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1/* | 1/* |
2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * |
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2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright --- 75 unchanged lines hidden (view full) --- 85 return 0; 86 } 87 88 }; 89 90 AtomicCPUPort icachePort; 91 AtomicCPUPort dcachePort; 92 | 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright --- 75 unchanged lines hidden (view full) --- 97 return 0; 98 } 99 100 }; 101 102 AtomicCPUPort icachePort; 103 AtomicCPUPort dcachePort; 104 |
93 CpuPort physmemPort; 94 bool hasPhysMemPort; | 105 bool fastmem; |
95 Request ifetch_req; 96 Request data_read_req; 97 Request data_write_req; 98 99 bool dcache_access; 100 Tick dcache_latency; 101 102 Range<Addr> physMemAddr; 103 104 protected: 105 106 /** Return a reference to the data port. */ 107 virtual CpuPort &getDataPort() { return dcachePort; } 108 109 /** Return a reference to the instruction port. */ 110 virtual CpuPort &getInstPort() { return icachePort; } 111 112 public: 113 | 106 Request ifetch_req; 107 Request data_read_req; 108 Request data_write_req; 109 110 bool dcache_access; 111 Tick dcache_latency; 112 113 Range<Addr> physMemAddr; 114 115 protected: 116 117 /** Return a reference to the data port. */ 118 virtual CpuPort &getDataPort() { return dcachePort; } 119 120 /** Return a reference to the instruction port. */ 121 virtual CpuPort &getInstPort() { return icachePort; } 122 123 public: 124 |
114 /** 115 * Override the getMasterPort of the BaseCPU so that we can 116 * provide the physmemPort, unique to the Atomic CPU. 117 */ 118 virtual MasterPort &getMasterPort(const std::string &if_name, 119 int idx = -1); 120 | |
121 virtual void serialize(std::ostream &os); 122 virtual void unserialize(Checkpoint *cp, const std::string §ion); 123 virtual void resume(); 124 125 void switchOut(); 126 void takeOverFrom(BaseCPU *oldCPU); 127 128 virtual void activateContext(ThreadID thread_num, int delay); --- 15 unchanged lines hidden --- | 125 virtual void serialize(std::ostream &os); 126 virtual void unserialize(Checkpoint *cp, const std::string §ion); 127 virtual void resume(); 128 129 void switchOut(); 130 void takeOverFrom(BaseCPU *oldCPU); 131 132 virtual void activateContext(ThreadID thread_num, int delay); --- 15 unchanged lines hidden --- |