1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

--- 75 unchanged lines hidden (view full) ---

85 return 0;
86 }
87
88 };
89
90 AtomicCPUPort icachePort;
91 AtomicCPUPort dcachePort;
92
93 CpuPort physmemPort;
94 bool hasPhysMemPort;
95 Request ifetch_req;
96 Request data_read_req;
97 Request data_write_req;
98
99 bool dcache_access;
100 Tick dcache_latency;
101
102 Range<Addr> physMemAddr;
103
104 protected:
105
106 /** Return a reference to the data port. */
107 virtual CpuPort &getDataPort() { return dcachePort; }
108
109 /** Return a reference to the instruction port. */
110 virtual CpuPort &getInstPort() { return icachePort; }
111
112 public:
113
114 /**
115 * Override the getMasterPort of the BaseCPU so that we can
116 * provide the physmemPort, unique to the Atomic CPU.
117 */
118 virtual MasterPort &getMasterPort(const std::string &if_name,
119 int idx = -1);
120
121 virtual void serialize(std::ostream &os);
122 virtual void unserialize(Checkpoint *cp, const std::string &section);
123 virtual void resume();
124
125 void switchOut();
126 void takeOverFrom(BaseCPU *oldCPU);
127
128 virtual void activateContext(ThreadID thread_num, int delay);

--- 15 unchanged lines hidden ---