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1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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59 const int width;
60 bool locked;
61 const bool simulate_data_stalls;
62 const bool simulate_inst_stalls;
63
64 // main simulation loop (one cycle)
65 void tick();
66
67 class CpuPort : public Port
68 {
69 public:
70
71 CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu)
72 : Port(_name, _cpu), cpu(_cpu)
73 { }
74
75 bool snoopRangeSent;
76
77 protected:
78
79 AtomicSimpleCPU *cpu;
80
81 virtual bool recvTiming(PacketPtr pkt);
82
83 virtual Tick recvAtomic(PacketPtr pkt);
84
85 virtual void recvFunctional(PacketPtr pkt);
86
87 virtual void recvStatusChange(Status status);
88
89 virtual void recvRetry();
90
91 virtual void getDeviceAddressRanges(AddrRangeList &resp,
92 bool &snoop)
93 { resp.clear(); snoop = true; }
94
95 };
96 CpuPort icachePort;
97
98 CpuPort dcachePort;
99
100 CpuPort physmemPort;
101 bool hasPhysMemPort;
102 Request ifetch_req;
103 Request data_read_req;
104 Request data_write_req;
105
106 bool dcache_access;

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