1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
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52 TickEvent(AtomicSimpleCPU *c);
53 void process();
54 const char *description() const;
55 };
56
57 TickEvent tickEvent;
58
59 const int width;
60 const bool simulate_data_stalls;
61 const bool simulate_inst_stalls;
62
63 // main simulation loop (one cycle)
64 void tick();
65
66 class CpuPort : public Port
67 {
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2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
--- 43 unchanged lines hidden (view full) ---
52 TickEvent(AtomicSimpleCPU *c);
53 void process();
54 const char *description() const;
55 };
56
57 TickEvent tickEvent;
58
59 const int width;
60 const bool simulate_data_stalls;
61 const bool simulate_inst_stalls;
62
63 // main simulation loop (one cycle)
64 void tick();
65
66 class CpuPort : public Port
67 {
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