1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
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79
80 class CpuPort : public Port
81 {
82
83 AtomicSimpleCPU *cpu;
84
85 public:
86
87 CpuPort(AtomicSimpleCPU *_cpu)
88 : cpu(_cpu)
89 { }
90
91 protected:
92
93 virtual bool recvTiming(Packet *pkt);
94
95 virtual Tick recvAtomic(Packet *pkt);
96
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2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
--- 70 unchanged lines hidden (view full) ---
79
80 class CpuPort : public Port
81 {
82
83 AtomicSimpleCPU *cpu;
84
85 public:
86
87 CpuPort(AtomicSimpleCPU *_cpu)
88 : cpu(_cpu)
89 { }
90
91 protected:
92
93 virtual bool recvTiming(Packet *pkt);
94
95 virtual Tick recvAtomic(Packet *pkt);
96
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