atomic.cc (9814:7ad2b0186a32) atomic.cc (9837:13a21202375d)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 161 unchanged lines hidden (view full) ---

170
171 assert(!threadContexts.empty());
172 if (threadContexts.size() > 1)
173 fatal("The atomic CPU only supports one thread.\n");
174
175 if (thread->status() == ThreadContext::Active) {
176 schedule(tickEvent, nextCycle());
177 _status = BaseSimpleCPU::Running;
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 161 unchanged lines hidden (view full) ---

170
171 assert(!threadContexts.empty());
172 if (threadContexts.size() > 1)
173 fatal("The atomic CPU only supports one thread.\n");
174
175 if (thread->status() == ThreadContext::Active) {
176 schedule(tickEvent, nextCycle());
177 _status = BaseSimpleCPU::Running;
178 notIdleFraction = 1;
178 } else {
179 _status = BaseSimpleCPU::Idle;
179 } else {
180 _status = BaseSimpleCPU::Idle;
181 notIdleFraction = 0;
180 }
181
182 system->totalNumInsts = 0;
183}
184
185bool
186AtomicSimpleCPU::tryCompleteDrain()
187{

--- 51 unchanged lines hidden (view full) ---

239 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
240
241 assert(thread_num == 0);
242 assert(thread);
243
244 assert(_status == Idle);
245 assert(!tickEvent.scheduled());
246
182 }
183
184 system->totalNumInsts = 0;
185}
186
187bool
188AtomicSimpleCPU::tryCompleteDrain()
189{

--- 51 unchanged lines hidden (view full) ---

241 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
242
243 assert(thread_num == 0);
244 assert(thread);
245
246 assert(_status == Idle);
247 assert(!tickEvent.scheduled());
248
247 notIdleFraction++;
249 notIdleFraction = 1;
248 numCycles += ticksToCycles(thread->lastActivate - thread->lastSuspend);
249
250 //Make sure ticks are still on multiples of cycles
251 schedule(tickEvent, clockEdge(delay));
252 _status = BaseSimpleCPU::Running;
253}
254
255

--- 10 unchanged lines hidden (view full) ---

266
267 assert(_status == BaseSimpleCPU::Running);
268
269 // tick event may not be scheduled if this gets called from inside
270 // an instruction's execution, e.g. "quiesce"
271 if (tickEvent.scheduled())
272 deschedule(tickEvent);
273
250 numCycles += ticksToCycles(thread->lastActivate - thread->lastSuspend);
251
252 //Make sure ticks are still on multiples of cycles
253 schedule(tickEvent, clockEdge(delay));
254 _status = BaseSimpleCPU::Running;
255}
256
257

--- 10 unchanged lines hidden (view full) ---

268
269 assert(_status == BaseSimpleCPU::Running);
270
271 // tick event may not be scheduled if this gets called from inside
272 // an instruction's execution, e.g. "quiesce"
273 if (tickEvent.scheduled())
274 deschedule(tickEvent);
275
274 notIdleFraction--;
276 notIdleFraction = 0;
275 _status = Idle;
276}
277
278
279Fault
280AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
281 unsigned size, unsigned flags)
282{

--- 384 unchanged lines hidden --- 		277 _status = Idle;
278}
279
280
281Fault
282AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
283 unsigned size, unsigned flags)
284{

--- 384 unchanged lines hidden ---