atomic.cc (9647:5b6b315472e7) atomic.cc (9814:7ad2b0186a32)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 273 unchanged lines hidden (view full) ---

282{
283 // use the CPU's statically allocated read request and packet objects
284 Request *req = &data_read_req;
285
286 if (traceData) {
287 traceData->setAddr(addr);
288 }
289
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 273 unchanged lines hidden (view full) ---

282{
283 // use the CPU's statically allocated read request and packet objects
284 Request *req = &data_read_req;
285
286 if (traceData) {
287 traceData->setAddr(addr);
288 }
289
290 //The block size of our peer.
291 unsigned blockSize = dcachePort.peerBlockSize();
292 //The size of the data we're trying to read.
293 int fullSize = size;
294
295 //The address of the second part of this access if it needs to be split
296 //across a cache line boundary.
290 //The size of the data we're trying to read.
291 int fullSize = size;
292
293 //The address of the second part of this access if it needs to be split
294 //across a cache line boundary.
297 Addr secondAddr = roundDown(addr + size - 1, blockSize);
295 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
298
299 if (secondAddr > addr)
300 size = secondAddr - addr;
301
302 dcache_latency = 0;
303
304 while (1) {
305 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());

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370{
371 // use the CPU's statically allocated write request and packet objects
372 Request *req = &data_write_req;
373
374 if (traceData) {
375 traceData->setAddr(addr);
376 }
377
296
297 if (secondAddr > addr)
298 size = secondAddr - addr;
299
300 dcache_latency = 0;
301
302 while (1) {
303 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());

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368{
369 // use the CPU's statically allocated write request and packet objects
370 Request *req = &data_write_req;
371
372 if (traceData) {
373 traceData->setAddr(addr);
374 }
375
378 //The block size of our peer.
379 unsigned blockSize = dcachePort.peerBlockSize();
380 //The size of the data we're trying to read.
381 int fullSize = size;
382
383 //The address of the second part of this access if it needs to be split
384 //across a cache line boundary.
376 //The size of the data we're trying to read.
377 int fullSize = size;
378
379 //The address of the second part of this access if it needs to be split
380 //across a cache line boundary.
385 Addr secondAddr = roundDown(addr + size - 1, blockSize);
381 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
386
387 if(secondAddr > addr)
388 size = secondAddr - addr;
389
390 dcache_latency = 0;
391
392 while(1) {
393 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());

--- 277 unchanged lines hidden --- 		382
383 if(secondAddr > addr)
384 size = secondAddr - addr;
385
386 dcache_latency = 0;
387
388 while(1) {
389 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());

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