atomic.cc (9524:d6ffa982a68b) | atomic.cc (9647:5b6b315472e7) |
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1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 30 unchanged lines hidden (view full) --- 39 * 40 * Authors: Steve Reinhardt 41 */ 42 43#include "arch/locked_mem.hh" 44#include "arch/mmapped_ipr.hh" 45#include "arch/utility.hh" 46#include "base/bigint.hh" | 1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 30 unchanged lines hidden (view full) --- 39 * 40 * Authors: Steve Reinhardt 41 */ 42 43#include "arch/locked_mem.hh" 44#include "arch/mmapped_ipr.hh" 45#include "arch/utility.hh" 46#include "base/bigint.hh" |
47#include "base/output.hh" |
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47#include "config/the_isa.hh" 48#include "cpu/simple/atomic.hh" 49#include "cpu/exetrace.hh" 50#include "debug/Drain.hh" 51#include "debug/ExecFaulting.hh" 52#include "debug/SimpleCPU.hh" 53#include "mem/packet.hh" 54#include "mem/packet_access.hh" --- 49 unchanged lines hidden (view full) --- 104 105AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 106 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 107 simulate_data_stalls(p->simulate_data_stalls), 108 simulate_inst_stalls(p->simulate_inst_stalls), 109 drain_manager(NULL), 110 icachePort(name() + ".icache_port", this), 111 dcachePort(name() + ".dcache_port", this), | 48#include "config/the_isa.hh" 49#include "cpu/simple/atomic.hh" 50#include "cpu/exetrace.hh" 51#include "debug/Drain.hh" 52#include "debug/ExecFaulting.hh" 53#include "debug/SimpleCPU.hh" 54#include "mem/packet.hh" 55#include "mem/packet_access.hh" --- 49 unchanged lines hidden (view full) --- 105 106AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 107 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 108 simulate_data_stalls(p->simulate_data_stalls), 109 simulate_inst_stalls(p->simulate_inst_stalls), 110 drain_manager(NULL), 111 icachePort(name() + ".icache_port", this), 112 dcachePort(name() + ".dcache_port", this), |
112 fastmem(p->fastmem) | 113 fastmem(p->fastmem), 114 simpoint(p->simpoint_profile), 115 intervalSize(p->simpoint_interval), 116 intervalCount(0), 117 intervalDrift(0), 118 simpointStream(NULL), 119 currentBBV(0, 0), 120 currentBBVInstCount(0) |
113{ 114 _status = Idle; | 121{ 122 _status = Idle; |
123 124 if (simpoint) { 125 simpointStream = simout.create(p->simpoint_profile_file, false); 126 } |
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115} 116 117 118AtomicSimpleCPU::~AtomicSimpleCPU() 119{ 120 if (tickEvent.scheduled()) { 121 deschedule(tickEvent); 122 } | 127} 128 129 130AtomicSimpleCPU::~AtomicSimpleCPU() 131{ 132 if (tickEvent.scheduled()) { 133 deschedule(tickEvent); 134 } |
135 if (simpointStream) { 136 simout.close(simpointStream); 137 } |
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123} 124 125unsigned int 126AtomicSimpleCPU::drain(DrainManager *dm) 127{ 128 assert(!drain_manager); 129 if (switchedOut()) 130 return 0; --- 398 unchanged lines hidden (view full) --- 529 postExecute(); 530 } 531 532 // @todo remove me after debugging with legion done 533 if (curStaticInst && (!curStaticInst->isMicroop() || 534 curStaticInst->isFirstMicroop())) 535 instCnt++; 536 | 138} 139 140unsigned int 141AtomicSimpleCPU::drain(DrainManager *dm) 142{ 143 assert(!drain_manager); 144 if (switchedOut()) 145 return 0; --- 398 unchanged lines hidden (view full) --- 544 postExecute(); 545 } 546 547 // @todo remove me after debugging with legion done 548 if (curStaticInst && (!curStaticInst->isMicroop() || 549 curStaticInst->isFirstMicroop())) 550 instCnt++; 551 |
552 // profile for SimPoints if enabled and macro inst is finished 553 if (simpoint && curStaticInst && (fault == NoFault) && 554 (!curStaticInst->isMicroop() || 555 curStaticInst->isLastMicroop())) { 556 profileSimPoint(); 557 } 558 |
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537 Tick stall_ticks = 0; 538 if (simulate_inst_stalls && icache_access) 539 stall_ticks += icache_latency; 540 541 if (simulate_data_stalls && dcache_access) 542 stall_ticks += dcache_latency; 543 544 if (stall_ticks) { --- 22 unchanged lines hidden (view full) --- 567 568 569void 570AtomicSimpleCPU::printAddr(Addr a) 571{ 572 dcachePort.printAddr(a); 573} 574 | 559 Tick stall_ticks = 0; 560 if (simulate_inst_stalls && icache_access) 561 stall_ticks += icache_latency; 562 563 if (simulate_data_stalls && dcache_access) 564 stall_ticks += dcache_latency; 565 566 if (stall_ticks) { --- 22 unchanged lines hidden (view full) --- 589 590 591void 592AtomicSimpleCPU::printAddr(Addr a) 593{ 594 dcachePort.printAddr(a); 595} 596 |
597void 598AtomicSimpleCPU::profileSimPoint() 599{ 600 if (!currentBBVInstCount) 601 currentBBV.first = thread->pcState().instAddr(); |
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575 | 602 |
603 ++intervalCount; 604 ++currentBBVInstCount; 605 606 // If inst is control inst, assume end of basic block. 607 if (curStaticInst->isControl()) { 608 currentBBV.second = thread->pcState().instAddr(); 609 610 auto map_itr = bbMap.find(currentBBV); 611 if (map_itr == bbMap.end()){ 612 // If a new (previously unseen) basic block is found, 613 // add a new unique id, record num of insts and insert into bbMap. 614 BBInfo info; 615 info.id = bbMap.size() + 1; 616 info.insts = currentBBVInstCount; 617 info.count = currentBBVInstCount; 618 bbMap.insert(std::make_pair(currentBBV, info)); 619 } else { 620 // If basic block is seen before, just increment the count by the 621 // number of insts in basic block. 622 BBInfo& info = map_itr->second; 623 assert(info.insts == currentBBVInstCount); 624 info.count += currentBBVInstCount; 625 } 626 currentBBVInstCount = 0; 627 628 // Reached end of interval if the sum of the current inst count 629 // (intervalCount) and the excessive inst count from the previous 630 // interval (intervalDrift) is greater than/equal to the interval size. 631 if (intervalCount + intervalDrift >= intervalSize) { 632 // summarize interval and display BBV info 633 std::vector<pair<uint64_t, uint64_t> > counts; 634 for (auto map_itr = bbMap.begin(); map_itr != bbMap.end(); 635 ++map_itr) { 636 BBInfo& info = map_itr->second; 637 if (info.count != 0) { 638 counts.push_back(std::make_pair(info.id, info.count)); 639 info.count = 0; 640 } 641 } 642 std::sort(counts.begin(), counts.end()); 643 644 // Print output BBV info 645 *simpointStream << "T"; 646 for (auto cnt_itr = counts.begin(); cnt_itr != counts.end(); 647 ++cnt_itr) { 648 *simpointStream << ":" << cnt_itr->first 649 << ":" << cnt_itr->second << " "; 650 } 651 *simpointStream << "\n"; 652 653 intervalDrift = (intervalCount + intervalDrift) - intervalSize; 654 intervalCount = 0; 655 } 656 } 657} 658 |
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576//////////////////////////////////////////////////////////////////////// 577// 578// AtomicSimpleCPU Simulation Object 579// 580AtomicSimpleCPU * 581AtomicSimpleCPUParams::create() 582{ 583 numThreads = 1; 584 if (!FullSystem && workload.size() != 1) 585 panic("only one workload allowed"); 586 return new AtomicSimpleCPU(this); 587} | 659//////////////////////////////////////////////////////////////////////// 660// 661// AtomicSimpleCPU Simulation Object 662// 663AtomicSimpleCPU * 664AtomicSimpleCPUParams::create() 665{ 666 numThreads = 1; 667 if (!FullSystem && workload.size() != 1) 668 panic("only one workload allowed"); 669 return new AtomicSimpleCPU(this); 670} |