atomic.cc (9443:0cb3209bc5c7) atomic.cc (9448:569d1e8f74e4)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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127 deschedule(tickEvent);
128 }
129}
130
131unsigned int
132AtomicSimpleCPU::drain(DrainManager *dm)
133{
134 assert(!drain_manager);
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 118 unchanged lines hidden (view full) ---

127 deschedule(tickEvent);
128 }
129}
130
131unsigned int
132AtomicSimpleCPU::drain(DrainManager *dm)
133{
134 assert(!drain_manager);
135 if (_status == SwitchedOut)
135 if (switchedOut())
136 return 0;
137
138 if (!isDrained()) {
139 DPRINTF(Drain, "Requesting drain: %s\n", pcState());
140 drain_manager = dm;
141 return 1;
142 } else {
143 if (tickEvent.scheduled())
144 deschedule(tickEvent);
145
146 DPRINTF(Drain, "Not executing microcode, no need to drain.\n");
147 return 0;
148 }
149}
150
151void
152AtomicSimpleCPU::drainResume()
153{
136 return 0;
137
138 if (!isDrained()) {
139 DPRINTF(Drain, "Requesting drain: %s\n", pcState());
140 drain_manager = dm;
141 return 1;
142 } else {
143 if (tickEvent.scheduled())
144 deschedule(tickEvent);
145
146 DPRINTF(Drain, "Not executing microcode, no need to drain.\n");
147 return 0;
148 }
149}
150
151void
152AtomicSimpleCPU::drainResume()
153{
154 assert(!tickEvent.scheduled());
154 assert(!drain_manager);
155 assert(!drain_manager);
155 if (_status == Idle || _status == SwitchedOut)
156 if (switchedOut())
156 return;
157
158 DPRINTF(SimpleCPU, "Resume\n");
159 if (system->getMemoryMode() != Enums::atomic) {
160 fatal("The atomic CPU requires the memory system to be in "
161 "'atomic' mode.\n");
162 }
163
157 return;
158
159 DPRINTF(SimpleCPU, "Resume\n");
160 if (system->getMemoryMode() != Enums::atomic) {
161 fatal("The atomic CPU requires the memory system to be in "
162 "'atomic' mode.\n");
163 }
164
164 assert(!tickEvent.scheduled());
165 if (thread->status() == ThreadContext::Active)
165 assert(!threadContexts.empty());
166 if (threadContexts.size() > 1)
167 fatal("The atomic CPU only supports one thread.\n");
168
169 if (thread->status() == ThreadContext::Active) {
166 schedule(tickEvent, nextCycle());
170 schedule(tickEvent, nextCycle());
171 _status = BaseSimpleCPU::Running;
172 } else {
173 _status = BaseSimpleCPU::Idle;
174 }
167
168 system->totalNumInsts = 0;
169}
170
171bool
172AtomicSimpleCPU::tryCompleteDrain()
173{
174 if (!drain_manager)

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189void
190AtomicSimpleCPU::switchOut()
191{
192 BaseSimpleCPU::switchOut();
193
194 assert(!tickEvent.scheduled());
195 assert(_status == BaseSimpleCPU::Running || _status == Idle);
196 assert(isDrained());
175
176 system->totalNumInsts = 0;
177}
178
179bool
180AtomicSimpleCPU::tryCompleteDrain()
181{
182 if (!drain_manager)

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197void
198AtomicSimpleCPU::switchOut()
199{
200 BaseSimpleCPU::switchOut();
201
202 assert(!tickEvent.scheduled());
203 assert(_status == BaseSimpleCPU::Running || _status == Idle);
204 assert(isDrained());
197
198 _status = SwitchedOut;
199}
200
201
202void
203AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
204{
205 BaseSimpleCPU::takeOverFrom(oldCPU);
206
207 // The tick event should have been descheduled by drain()
208 assert(!tickEvent.scheduled());
209
205}
206
207
208void
209AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
210{
211 BaseSimpleCPU::takeOverFrom(oldCPU);
212
213 // The tick event should have been descheduled by drain()
214 assert(!tickEvent.scheduled());
215
210 assert(!threadContexts.empty());
211 if (threadContexts.size() > 1)
212 fatal("The atomic CPU only supports one thread.\n");
213
214 // If the ThreadContext is active, mark the CPU as running.
215 if (thread->status() == ThreadContext::Active)
216 _status = BaseSimpleCPU::Running;
217 else
218 _status = Idle;
219
220 ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
221 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
222 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
223}
224
225
226void
227AtomicSimpleCPU::activateContext(ThreadID thread_num, Cycles delay)

--- 365 unchanged lines hidden --- 		216 ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
217 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
218 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
219}
220
221
222void
223AtomicSimpleCPU::activateContext(ThreadID thread_num, Cycles delay)

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