atomic.cc (9058:cc47e11ccec1) atomic.cc (9095:0e6bd7082fac)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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100 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
101 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
102}
103
104AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
105 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
106 simulate_data_stalls(p->simulate_data_stalls),
107 simulate_inst_stalls(p->simulate_inst_stalls),
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 91 unchanged lines hidden (view full) ---

100 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
101 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
102}
103
104AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
105 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
106 simulate_data_stalls(p->simulate_data_stalls),
107 simulate_inst_stalls(p->simulate_inst_stalls),
108 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
108 icachePort(name() + ".icache_port", this),
109 dcachePort(name() + ".dcache_port", this),
109 fastmem(p->fastmem)
110{
111 _status = Idle;
112}
113
114
115AtomicSimpleCPU::~AtomicSimpleCPU()
116{

--- 445 unchanged lines hidden --- 		110 fastmem(p->fastmem)
111{
112 _status = Idle;
113}
114
115
116AtomicSimpleCPU::~AtomicSimpleCPU()
117{

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