atomic.cc (8931:7a1dfb191e3f) atomic.cc (8949:3fa1ee293096)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 258 unchanged lines hidden (view full) ---

267 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
268
269 // translate to physical address
270 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
271
272 // Now do the access.
273 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
274 Packet pkt = Packet(req,
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 258 unchanged lines hidden (view full) ---

267 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
268
269 // translate to physical address
270 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
271
272 // Now do the access.
273 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
274 Packet pkt = Packet(req,
275 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
276 Packet::Broadcast);
275 req->isLLSC() ? MemCmd::LoadLockedReq :
276 MemCmd::ReadReq);
277 pkt.dataStatic(data);
278
279 if (req->isMmappedIpr())
280 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
281 else {
282 if (fastmem && system->isMemAddr(pkt.getAddr()))
283 system->getPhysMem().access(&pkt);
284 else

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369 cmd = MemCmd::SwapReq;
370 if (req->isCondSwap()) {
371 assert(res);
372 req->setExtraData(*res);
373 }
374 }
375
376 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
277 pkt.dataStatic(data);
278
279 if (req->isMmappedIpr())
280 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
281 else {
282 if (fastmem && system->isMemAddr(pkt.getAddr()))
283 system->getPhysMem().access(&pkt);
284 else

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369 cmd = MemCmd::SwapReq;
370 if (req->isCondSwap()) {
371 assert(res);
372 req->setExtraData(*res);
373 }
374 }
375
376 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
377 Packet pkt = Packet(req, cmd, Packet::Broadcast);
377 Packet pkt = Packet(req, cmd);
378 pkt.dataStatic(data);
379
380 if (req->isMmappedIpr()) {
381 dcache_latency +=
382 TheISA::handleIprWrite(thread->getTC(), &pkt);
383 } else {
384 if (fastmem && system->isMemAddr(pkt.getAddr()))
385 system->getPhysMem().access(&pkt);

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468 // This is commented out because the predecoder would act like
469 // a tiny cache otherwise. It wouldn't be flushed when needed
470 // like the I cache. It should be flushed, and when that works
471 // this code should be uncommented.
472 //Fetch more instruction memory if necessary
473 //if(predecoder.needMoreBytes())
474 //{
475 icache_access = true;
378 pkt.dataStatic(data);
379
380 if (req->isMmappedIpr()) {
381 dcache_latency +=
382 TheISA::handleIprWrite(thread->getTC(), &pkt);
383 } else {
384 if (fastmem && system->isMemAddr(pkt.getAddr()))
385 system->getPhysMem().access(&pkt);

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468 // This is commented out because the predecoder would act like
469 // a tiny cache otherwise. It wouldn't be flushed when needed
470 // like the I cache. It should be flushed, and when that works
471 // this code should be uncommented.
472 //Fetch more instruction memory if necessary
473 //if(predecoder.needMoreBytes())
474 //{
475 icache_access = true;
476 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
477 Packet::Broadcast);
476 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq);
478 ifetch_pkt.dataStatic(&inst);
479
480 if (fastmem && system->isMemAddr(ifetch_pkt.getAddr()))
481 system->getPhysMem().access(&ifetch_pkt);
482 else
483 icache_latency = icachePort.sendAtomic(&ifetch_pkt);
484
485 assert(!ifetch_pkt.isError());

--- 77 unchanged lines hidden --- 		477 ifetch_pkt.dataStatic(&inst);
478
479 if (fastmem && system->isMemAddr(ifetch_pkt.getAddr()))
480 system->getPhysMem().access(&ifetch_pkt);
481 else
482 icache_latency = icachePort.sendAtomic(&ifetch_pkt);
483
484 assert(!ifetch_pkt.isError());

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