atomic.cc (8922:17f037ad8918) atomic.cc (8926:570b44fe6e04)
1/*
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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34#include "base/bigint.hh"
35#include "config/the_isa.hh"
36#include "cpu/simple/atomic.hh"
37#include "cpu/exetrace.hh"
38#include "debug/ExecFaulting.hh"
39#include "debug/SimpleCPU.hh"
40#include "mem/packet.hh"
41#include "mem/packet_access.hh"
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright

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46#include "base/bigint.hh"
47#include "config/the_isa.hh"
48#include "cpu/simple/atomic.hh"
49#include "cpu/exetrace.hh"
50#include "debug/ExecFaulting.hh"
51#include "debug/SimpleCPU.hh"
52#include "mem/packet.hh"
53#include "mem/packet_access.hh"
54#include "mem/physical.hh"
42#include "params/AtomicSimpleCPU.hh"
43#include "sim/faults.hh"
44#include "sim/system.hh"
45#include "sim/full_system.hh"
46
47using namespace std;
48using namespace TheISA;
49

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60}
61
62const char *
63AtomicSimpleCPU::TickEvent::description() const
64{
65 return "AtomicSimpleCPU tick";
66}
67
55#include "params/AtomicSimpleCPU.hh"
56#include "sim/faults.hh"
57#include "sim/system.hh"
58#include "sim/full_system.hh"
59
60using namespace std;
61using namespace TheISA;
62

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73}
74
75const char *
76AtomicSimpleCPU::TickEvent::description() const
77{
78 return "AtomicSimpleCPU tick";
79}
80
68MasterPort &
69AtomicSimpleCPU::getMasterPort(const string &if_name, int idx)
70{
71 if (if_name == "physmem_port") {
72 hasPhysMemPort = true;
73 return physmemPort;
74 } else {
75 return BaseCPU::getMasterPort(if_name, idx);
76 }
77}
78
79void
80AtomicSimpleCPU::init()
81{
82 BaseCPU::init();
83
84 // Initialise the ThreadContext's memory proxies
85 tcBase()->initMemProxies(tcBase());
86
87 if (FullSystem) {
88 ThreadID size = threadContexts.size();
89 for (ThreadID i = 0; i < size; ++i) {
90 ThreadContext *tc = threadContexts[i];
91 // initialize CPU, including PC
92 TheISA::initCPU(tc, tc->contextId());
93 }
94 }
95
81void
82AtomicSimpleCPU::init()
83{
84 BaseCPU::init();
85
86 // Initialise the ThreadContext's memory proxies
87 tcBase()->initMemProxies(tcBase());
88
89 if (FullSystem) {
90 ThreadID size = threadContexts.size();
91 for (ThreadID i = 0; i < size; ++i) {
92 ThreadContext *tc = threadContexts[i];
93 // initialize CPU, including PC
94 TheISA::initCPU(tc, tc->contextId());
95 }
96 }
97
96 if (hasPhysMemPort) {
97 AddrRangeList pmAddrList = physmemPort.getSlavePort().getAddrRanges();
98 if (fastmem) {
99 AddrRangeList pmAddrList = system->physmem->getAddrRanges();
98 physMemAddr = *pmAddrList.begin();
99 }
100 // Atomic doesn't do MT right now, so contextId == threadId
101 ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
102 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
103 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
104}
105
106AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
107 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
108 simulate_data_stalls(p->simulate_data_stalls),
109 simulate_inst_stalls(p->simulate_inst_stalls),
110 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
100 physMemAddr = *pmAddrList.begin();
101 }
102 // Atomic doesn't do MT right now, so contextId == threadId
103 ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
104 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
105 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
106}
107
108AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
109 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
110 simulate_data_stalls(p->simulate_data_stalls),
111 simulate_inst_stalls(p->simulate_inst_stalls),
112 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
111 physmemPort(name() + "-iport", this), hasPhysMemPort(false)
113 fastmem(p->fastmem)
112{
113 _status = Idle;
114}
115
116
117AtomicSimpleCPU::~AtomicSimpleCPU()
118{
119 if (tickEvent.scheduled()) {

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276 Packet pkt = Packet(req,
277 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
278 Packet::Broadcast);
279 pkt.dataStatic(data);
280
281 if (req->isMmappedIpr())
282 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
283 else {
114{
115 _status = Idle;
116}
117
118
119AtomicSimpleCPU::~AtomicSimpleCPU()
120{
121 if (tickEvent.scheduled()) {

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278 Packet pkt = Packet(req,
279 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
280 Packet::Broadcast);
281 pkt.dataStatic(data);
282
283 if (req->isMmappedIpr())
284 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
285 else {
284 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
285 dcache_latency += physmemPort.sendAtomic(&pkt);
286 if (fastmem && pkt.getAddr() == physMemAddr)
287 dcache_latency += system->physmem->doAtomicAccess(&pkt);
286 else
287 dcache_latency += dcachePort.sendAtomic(&pkt);
288 }
289 dcache_access = true;
290
291 assert(!pkt.isError());
292
293 if (req->isLLSC()) {

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378 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
379 Packet pkt = Packet(req, cmd, Packet::Broadcast);
380 pkt.dataStatic(data);
381
382 if (req->isMmappedIpr()) {
383 dcache_latency +=
384 TheISA::handleIprWrite(thread->getTC(), &pkt);
385 } else {
288 else
289 dcache_latency += dcachePort.sendAtomic(&pkt);
290 }
291 dcache_access = true;
292
293 assert(!pkt.isError());
294
295 if (req->isLLSC()) {

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380 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
381 Packet pkt = Packet(req, cmd, Packet::Broadcast);
382 pkt.dataStatic(data);
383
384 if (req->isMmappedIpr()) {
385 dcache_latency +=
386 TheISA::handleIprWrite(thread->getTC(), &pkt);
387 } else {
386 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
387 dcache_latency += physmemPort.sendAtomic(&pkt);
388 if (fastmem && pkt.getAddr() == physMemAddr)
389 dcache_latency += system->physmem->doAtomicAccess(&pkt);
388 else
389 dcache_latency += dcachePort.sendAtomic(&pkt);
390 }
391 dcache_access = true;
392 assert(!pkt.isError());
393
394 if (req->isSwap()) {
395 assert(res);

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474 //Fetch more instruction memory if necessary
475 //if(predecoder.needMoreBytes())
476 //{
477 icache_access = true;
478 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
479 Packet::Broadcast);
480 ifetch_pkt.dataStatic(&inst);
481
390 else
391 dcache_latency += dcachePort.sendAtomic(&pkt);
392 }
393 dcache_access = true;
394 assert(!pkt.isError());
395
396 if (req->isSwap()) {
397 assert(res);

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476 //Fetch more instruction memory if necessary
477 //if(predecoder.needMoreBytes())
478 //{
479 icache_access = true;
480 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
481 Packet::Broadcast);
482 ifetch_pkt.dataStatic(&inst);
483
482 if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
483 icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
484 if (fastmem && ifetch_pkt.getAddr() == physMemAddr)
485 icache_latency =
486 system->physmem->doAtomicAccess(&ifetch_pkt);
484 else
485 icache_latency = icachePort.sendAtomic(&ifetch_pkt);
486
487 assert(!ifetch_pkt.isError());
488
489 // ifetch_req is initialized to read the instruction directly
490 // into the CPU object's inst field.
491 //}

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488 icache_latency = icachePort.sendAtomic(&ifetch_pkt);
489
490 assert(!ifetch_pkt.isError());
491
492 // ifetch_req is initialized to read the instruction directly
493 // into the CPU object's inst field.
494 //}

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