atomic.cc (8706:b1838faf3bcc) atomic.cc (8707:489489c67fd9)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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102 physMemAddr = *pmAddrList.begin();
103 }
104 // Atomic doesn't do MT right now, so contextId == threadId
105 ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
106 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
107 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
108}
109
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 93 unchanged lines hidden (view full) ---

102 physMemAddr = *pmAddrList.begin();
103 }
104 // Atomic doesn't do MT right now, so contextId == threadId
105 ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
106 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
107 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
108}
109
110bool
111AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
112{
113 panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
114 return true;
115}
116
117Tick
118AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
119{
120 //Snooping a coherence request, just return
121 return 0;
122}
123
124void
125AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
126{
127 //No internal storage to update, just return
128 return;
129}
130
131void
132AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
133{
134 if (status == RangeChange) {
135 if (!snoopRangeSent) {
136 snoopRangeSent = true;
137 sendStatusChange(Port::RangeChange);
138 }
139 return;
140 }
141
142 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
143}
144
145void
146AtomicSimpleCPU::CpuPort::recvRetry()
147{
148 panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
149}
150
151AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
152 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
153 simulate_data_stalls(p->simulate_data_stalls),
154 simulate_inst_stalls(p->simulate_inst_stalls),
155 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
156 physmemPort(name() + "-iport", this), hasPhysMemPort(false)
157{
158 _status = Idle;
110AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
111 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
112 simulate_data_stalls(p->simulate_data_stalls),
113 simulate_inst_stalls(p->simulate_inst_stalls),
114 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
115 physmemPort(name() + "-iport", this), hasPhysMemPort(false)
116{
117 _status = Idle;
159
160 icachePort.snoopRangeSent = false;
161 dcachePort.snoopRangeSent = false;
162
163}
164
165
166AtomicSimpleCPU::~AtomicSimpleCPU()
167{
168 if (tickEvent.scheduled()) {
169 deschedule(tickEvent);
170 }

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119
120
121AtomicSimpleCPU::~AtomicSimpleCPU()
122{
123 if (tickEvent.scheduled()) {
124 deschedule(tickEvent);
125 }

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