| atomic.cc (7897:d9e8b1fd1a9f) | atomic.cc (8105:906864dd0937) |
|---|---|
| 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 15 unchanged lines hidden (view full) --- 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#include "arch/locked_mem.hh" | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 15 unchanged lines hidden (view full) --- 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#include "arch/locked_mem.hh" |
| 32#include "arch/mmaped_ipr.hh" | 32#include "arch/mmapped_ipr.hh" |
| 33#include "arch/utility.hh" 34#include "base/bigint.hh" 35#include "config/the_isa.hh" 36#include "cpu/exetrace.hh" 37#include "cpu/simple/atomic.hh" 38#include "mem/packet.hh" 39#include "mem/packet_access.hh" 40#include "params/AtomicSimpleCPU.hh" --- 288 unchanged lines hidden (view full) --- 329 330 // Now do the access. 331 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 332 Packet pkt = Packet(req, 333 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq, 334 Packet::Broadcast); 335 pkt.dataStatic(data); 336 | 33#include "arch/utility.hh" 34#include "base/bigint.hh" 35#include "config/the_isa.hh" 36#include "cpu/exetrace.hh" 37#include "cpu/simple/atomic.hh" 38#include "mem/packet.hh" 39#include "mem/packet_access.hh" 40#include "params/AtomicSimpleCPU.hh" --- 288 unchanged lines hidden (view full) --- 329 330 // Now do the access. 331 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 332 Packet pkt = Packet(req, 333 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq, 334 Packet::Broadcast); 335 pkt.dataStatic(data); 336 |
| 337 if (req->isMmapedIpr()) | 337 if (req->isMmappedIpr()) |
| 338 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 339 else { 340 if (hasPhysMemPort && pkt.getAddr() == physMemAddr) 341 dcache_latency += physmemPort.sendAtomic(&pkt); 342 else 343 dcache_latency += dcachePort.sendAtomic(&pkt); 344 } 345 dcache_access = true; --- 150 unchanged lines hidden (view full) --- 496 req->setExtraData(*res); 497 } 498 } 499 500 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 501 Packet pkt = Packet(req, cmd, Packet::Broadcast); 502 pkt.dataStatic(data); 503 | 338 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 339 else { 340 if (hasPhysMemPort && pkt.getAddr() == physMemAddr) 341 dcache_latency += physmemPort.sendAtomic(&pkt); 342 else 343 dcache_latency += dcachePort.sendAtomic(&pkt); 344 } 345 dcache_access = true; --- 150 unchanged lines hidden (view full) --- 496 req->setExtraData(*res); 497 } 498 } 499 500 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 501 Packet pkt = Packet(req, cmd, Packet::Broadcast); 502 pkt.dataStatic(data); 503 |
| 504 if (req->isMmapedIpr()) { | 504 if (req->isMmappedIpr()) { |
| 505 dcache_latency += 506 TheISA::handleIprWrite(thread->getTC(), &pkt); 507 } else { 508 if (hasPhysMemPort && pkt.getAddr() == physMemAddr) 509 dcache_latency += physmemPort.sendAtomic(&pkt); 510 else 511 dcache_latency += dcachePort.sendAtomic(&pkt); 512 } --- 247 unchanged lines hidden --- | 505 dcache_latency += 506 TheISA::handleIprWrite(thread->getTC(), &pkt); 507 } else { 508 if (hasPhysMemPort && pkt.getAddr() == physMemAddr) 509 dcache_latency += physmemPort.sendAtomic(&pkt); 510 else 511 dcache_latency += dcachePort.sendAtomic(&pkt); 512 } --- 247 unchanged lines hidden --- |