atomic.cc (7046:d21d575a6f99) atomic.cc (7518:917208416d2a)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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445 // use the CPU's statically allocated write request and packet objects
446 Request *req = &data_write_req;
447
448 if (traceData) {
449 traceData->setAddr(addr);
450 traceData->setData(data);
451 }
452
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 436 unchanged lines hidden (view full) ---

445 // use the CPU's statically allocated write request and packet objects
446 Request *req = &data_write_req;
447
448 if (traceData) {
449 traceData->setAddr(addr);
450 traceData->setData(data);
451 }
452
453 data = htog(data);
454
453 //The block size of our peer.
454 unsigned blockSize = dcachePort.peerBlockSize();
455 //The size of the data we're trying to read.
456 int dataSize = sizeof(T);
457
458 uint8_t * dataPtr = (uint8_t *)&data;
459
460 //The address of the second part of this access if it needs to be split

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491 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
492 Packet pkt = Packet(req, cmd, Packet::Broadcast);
493 pkt.dataStatic(dataPtr);
494
495 if (req->isMmapedIpr()) {
496 dcache_latency +=
497 TheISA::handleIprWrite(thread->getTC(), &pkt);
498 } else {
455 //The block size of our peer.
456 unsigned blockSize = dcachePort.peerBlockSize();
457 //The size of the data we're trying to read.
458 int dataSize = sizeof(T);
459
460 uint8_t * dataPtr = (uint8_t *)&data;
461
462 //The address of the second part of this access if it needs to be split

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493 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
494 Packet pkt = Packet(req, cmd, Packet::Broadcast);
495 pkt.dataStatic(dataPtr);
496
497 if (req->isMmapedIpr()) {
498 dcache_latency +=
499 TheISA::handleIprWrite(thread->getTC(), &pkt);
500 } else {
499 //XXX This needs to be outside of the loop in order to
500 //work properly for cache line boundary crossing
501 //accesses in transendian simulations.
502 data = htog(data);
503 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
504 dcache_latency += physmemPort.sendAtomic(&pkt);
505 else
506 dcache_latency += dcachePort.sendAtomic(&pkt);
507 }
508 dcache_access = true;
509 assert(!pkt.isError());
510

--- 225 unchanged lines hidden --- 		501 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
502 dcache_latency += physmemPort.sendAtomic(&pkt);
503 else
504 dcache_latency += dcachePort.sendAtomic(&pkt);
505 }
506 dcache_access = true;
507 assert(!pkt.isError());
508

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