atomic.cc (6227:a17798f2a52c) atomic.cc (6623:f7abbfd5a79f)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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319
320 while(1) {
321 req->setVirt(0, addr, dataSize, flags, thread->readPC());
322
323 // translate to physical address
324 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
325
326 // Now do the access.
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 310 unchanged lines hidden (view full) ---

319
320 while(1) {
321 req->setVirt(0, addr, dataSize, flags, thread->readPC());
322
323 // translate to physical address
324 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
325
326 // Now do the access.
327 if (fault == NoFault) {
327 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
328 Packet pkt = Packet(req,
329 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
330 Packet::Broadcast);
331 pkt.dataStatic(dataPtr);
332
333 if (req->isMmapedIpr())
334 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
335 else {

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476 } else if (req->isSwap()) {
477 cmd = MemCmd::SwapReq;
478 if (req->isCondSwap()) {
479 assert(res);
480 req->setExtraData(*res);
481 }
482 }
483
328 Packet pkt = Packet(req,
329 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
330 Packet::Broadcast);
331 pkt.dataStatic(dataPtr);
332
333 if (req->isMmapedIpr())
334 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
335 else {

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476 } else if (req->isSwap()) {
477 cmd = MemCmd::SwapReq;
478 if (req->isCondSwap()) {
479 assert(res);
480 req->setExtraData(*res);
481 }
482 }
483
484 if (do_access) {
484 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
485 Packet pkt = Packet(req, cmd, Packet::Broadcast);
486 pkt.dataStatic(dataPtr);
487
488 if (req->isMmapedIpr()) {
489 dcache_latency +=
490 TheISA::handleIprWrite(thread->getTC(), &pkt);
491 } else {
492 //XXX This needs to be outside of the loop in order to

--- 242 unchanged lines hidden --- 		485 Packet pkt = Packet(req, cmd, Packet::Broadcast);
486 pkt.dataStatic(dataPtr);
487
488 if (req->isMmapedIpr()) {
489 dcache_latency +=
490 TheISA::handleIprWrite(thread->getTC(), &pkt);
491 } else {
492 //XXX This needs to be outside of the loop in order to

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