atomic.cc (6102:7fbf97dc6540) | atomic.cc (6221:58a3c04e6344) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 66 unchanged lines hidden (view full) --- 75 panic("No Such Port\n"); 76} 77 78void 79AtomicSimpleCPU::init() 80{ 81 BaseCPU::init(); 82#if FULL_SYSTEM | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 66 unchanged lines hidden (view full) --- 75 panic("No Such Port\n"); 76} 77 78void 79AtomicSimpleCPU::init() 80{ 81 BaseCPU::init(); 82#if FULL_SYSTEM |
83 for (int i = 0; i < threadContexts.size(); ++i) { | 83 ThreadID size = threadContexts.size(); 84 for (ThreadID i = 0; i < size; ++i) { |
84 ThreadContext *tc = threadContexts[i]; 85 86 // initialize CPU, including PC 87 TheISA::initCPU(tc, tc->contextId()); 88 } 89#endif 90 if (hasPhysMemPort) { 91 bool snoop = false; --- 130 unchanged lines hidden (view full) --- 222AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 223{ 224 BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 225 226 assert(!tickEvent.scheduled()); 227 228 // if any of this CPU's ThreadContexts are active, mark the CPU as 229 // running and schedule its tick event. | 85 ThreadContext *tc = threadContexts[i]; 86 87 // initialize CPU, including PC 88 TheISA::initCPU(tc, tc->contextId()); 89 } 90#endif 91 if (hasPhysMemPort) { 92 bool snoop = false; --- 130 unchanged lines hidden (view full) --- 223AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 224{ 225 BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 226 227 assert(!tickEvent.scheduled()); 228 229 // if any of this CPU's ThreadContexts are active, mark the CPU as 230 // running and schedule its tick event. |
230 for (int i = 0; i < threadContexts.size(); ++i) { | 231 ThreadID size = threadContexts.size(); 232 for (ThreadID i = 0; i < size; ++i) { |
231 ThreadContext *tc = threadContexts[i]; 232 if (tc->status() == ThreadContext::Active && _status != Running) { 233 _status = Running; 234 schedule(tickEvent, nextCycle()); 235 break; 236 } 237 } 238 if (_status != Running) { --- 494 unchanged lines hidden --- | 233 ThreadContext *tc = threadContexts[i]; 234 if (tc->status() == ThreadContext::Active && _status != Running) { 235 _status = Running; 236 schedule(tickEvent, nextCycle()); 237 break; 238 } 239 } 240 if (_status != Running) { --- 494 unchanged lines hidden --- |