atomic.cc (6078:aae5ac55c749) atomic.cc (6102:7fbf97dc6540)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 310 unchanged lines hidden (view full) ---

319 req->setVirt(0, addr, dataSize, flags, thread->readPC());
320
321 // translate to physical address
322 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
323
324 // Now do the access.
325 if (fault == NoFault) {
326 Packet pkt = Packet(req,
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 310 unchanged lines hidden (view full) ---

319 req->setVirt(0, addr, dataSize, flags, thread->readPC());
320
321 // translate to physical address
322 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
323
324 // Now do the access.
325 if (fault == NoFault) {
326 Packet pkt = Packet(req,
327 req->isLlsc() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
327 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
328 Packet::Broadcast);
329 pkt.dataStatic(dataPtr);
330
331 if (req->isMmapedIpr())
332 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
333 else {
334 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
335 dcache_latency += physmemPort.sendAtomic(&pkt);
336 else
337 dcache_latency += dcachePort.sendAtomic(&pkt);
338 }
339 dcache_access = true;
340
341 assert(!pkt.isError());
342
328 Packet::Broadcast);
329 pkt.dataStatic(dataPtr);
330
331 if (req->isMmapedIpr())
332 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
333 else {
334 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
335 dcache_latency += physmemPort.sendAtomic(&pkt);
336 else
337 dcache_latency += dcachePort.sendAtomic(&pkt);
338 }
339 dcache_access = true;
340
341 assert(!pkt.isError());
342
343 if (req->isLlsc()) {
343 if (req->isLLSC()) {
344 TheISA::handleLockedRead(thread, req);
345 }
346 }
347
348 // This will need a new way to tell if it has a dcache attached.
349 if (req->isUncacheable())
350 recordEvent("Uncached Read");
351

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463 // translate to physical address
464 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write);
465
466 // Now do the access.
467 if (fault == NoFault) {
468 MemCmd cmd = MemCmd::WriteReq; // default
469 bool do_access = true; // flag to suppress cache access
470
344 TheISA::handleLockedRead(thread, req);
345 }
346 }
347
348 // This will need a new way to tell if it has a dcache attached.
349 if (req->isUncacheable())
350 recordEvent("Uncached Read");
351

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463 // translate to physical address
464 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write);
465
466 // Now do the access.
467 if (fault == NoFault) {
468 MemCmd cmd = MemCmd::WriteReq; // default
469 bool do_access = true; // flag to suppress cache access
470
471 if (req->isLlsc()) {
471 if (req->isLLSC()) {
472 cmd = MemCmd::StoreCondReq;
473 do_access = TheISA::handleLockedWrite(thread, req);
474 } else if (req->isSwap()) {
475 cmd = MemCmd::SwapReq;
476 if (req->isCondSwap()) {
477 assert(res);
478 req->setExtraData(*res);
479 }

--- 253 unchanged lines hidden --- 		472 cmd = MemCmd::StoreCondReq;
473 do_access = TheISA::handleLockedWrite(thread, req);
474 } else if (req->isSwap()) {
475 cmd = MemCmd::SwapReq;
476 if (req->isCondSwap()) {
477 assert(res);
478 req->setExtraData(*res);
479 }

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