atomic.cc (6076:e141cc7896ce) atomic.cc (6078:aae5ac55c749)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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148#if FULL_SYSTEM
149 // Update the ThreadContext's memory ports (Functional/Virtual
150 // Ports)
151 cpu->tcBase()->connectMemPorts(cpu->tcBase());
152#endif
153}
154
155AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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148#if FULL_SYSTEM
149 // Update the ThreadContext's memory ports (Functional/Virtual
150 // Ports)
151 cpu->tcBase()->connectMemPorts(cpu->tcBase());
152#endif
153}
154
155AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
156 : BaseSimpleCPU(p), tickEvent(this), width(p->width),
156 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
157 simulate_data_stalls(p->simulate_data_stalls),
158 simulate_inst_stalls(p->simulate_inst_stalls),
159 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
160 physmemPort(name() + "-iport", this), hasPhysMemPort(false)
161{
162 _status = Idle;
163
164 icachePort.snoopRangeSent = false;

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171{
172}
173
174void
175AtomicSimpleCPU::serialize(ostream &os)
176{
177 SimObject::State so_state = SimObject::getState();
178 SERIALIZE_ENUM(so_state);
157 simulate_data_stalls(p->simulate_data_stalls),
158 simulate_inst_stalls(p->simulate_inst_stalls),
159 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
160 physmemPort(name() + "-iport", this), hasPhysMemPort(false)
161{
162 _status = Idle;
163
164 icachePort.snoopRangeSent = false;

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171{
172}
173
174void
175AtomicSimpleCPU::serialize(ostream &os)
176{
177 SimObject::State so_state = SimObject::getState();
178 SERIALIZE_ENUM(so_state);
179 SERIALIZE_SCALAR(locked);
179 BaseSimpleCPU::serialize(os);
180 nameOut(os, csprintf("%s.tickEvent", name()));
181 tickEvent.serialize(os);
182}
183
184void
185AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
186{
187 SimObject::State so_state;
188 UNSERIALIZE_ENUM(so_state);
180 BaseSimpleCPU::serialize(os);
181 nameOut(os, csprintf("%s.tickEvent", name()));
182 tickEvent.serialize(os);
183}
184
185void
186AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
187{
188 SimObject::State so_state;
189 UNSERIALIZE_ENUM(so_state);
190 UNSERIALIZE_SCALAR(locked);
189 BaseSimpleCPU::unserialize(cp, section);
190 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
191}
192
193void
194AtomicSimpleCPU::resume()
195{
196 if (_status == Idle || _status == SwitchedOut)

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352 return fault;
353 //If we don't need to access a second cache line, stop now.
354 if (secondAddr <= addr)
355 {
356 data = gtoh(data);
357 if (traceData) {
358 traceData->setData(data);
359 }
191 BaseSimpleCPU::unserialize(cp, section);
192 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
193}
194
195void
196AtomicSimpleCPU::resume()
197{
198 if (_status == Idle || _status == SwitchedOut)

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354 return fault;
355 //If we don't need to access a second cache line, stop now.
356 if (secondAddr <= addr)
357 {
358 data = gtoh(data);
359 if (traceData) {
360 traceData->setData(data);
361 }
362 if (req->isLocked() && fault == NoFault) {
363 assert(!locked);
364 locked = true;
365 }
360 return fault;
361 }
362
363 /*
364 * Set up for accessing the second cache line.
365 */
366
367 //Move the pointer we're reading into to the correct location.

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513 if (fault != NoFault || secondAddr <= addr)
514 {
515 // If the write needs to have a fault on the access, consider
516 // calling changeStatus() and changing it to "bad addr write"
517 // or something.
518 if (traceData) {
519 traceData->setData(gtoh(data));
520 }
366 return fault;
367 }
368
369 /*
370 * Set up for accessing the second cache line.
371 */
372
373 //Move the pointer we're reading into to the correct location.

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519 if (fault != NoFault || secondAddr <= addr)
520 {
521 // If the write needs to have a fault on the access, consider
522 // calling changeStatus() and changing it to "bad addr write"
523 // or something.
524 if (traceData) {
525 traceData->setData(gtoh(data));
526 }
527 if (req->isLocked() && fault == NoFault) {
528 assert(locked);
529 locked = false;
530 }
521 return fault;
522 }
523
524 /*
525 * Set up for accessing the second cache line.
526 */
527
528 //Move the pointer we're reading into to the correct location.

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594
595void
596AtomicSimpleCPU::tick()
597{
598 DPRINTF(SimpleCPU, "Tick\n");
599
600 Tick latency = 0;
601
531 return fault;
532 }
533
534 /*
535 * Set up for accessing the second cache line.
536 */
537
538 //Move the pointer we're reading into to the correct location.

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604
605void
606AtomicSimpleCPU::tick()
607{
608 DPRINTF(SimpleCPU, "Tick\n");
609
610 Tick latency = 0;
611
602 for (int i = 0; i < width; ++i) {
612 for (int i = 0; i < width || locked; ++i) {
603 numCycles++;
604
605 if (!curStaticInst || !curStaticInst->isDelayedCommit())
606 checkForInterrupts();
607
608 checkPcEventQueue();
609
610 Fault fault = NoFault;

--- 112 unchanged lines hidden --- 		613 numCycles++;
614
615 if (!curStaticInst || !curStaticInst->isDelayedCommit())
616 checkForInterrupts();
617
618 checkPcEventQueue();
619
620 Fault fault = NoFault;

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