atomic.cc (6043:19852407f5c9) atomic.cc (6076:e141cc7896ce)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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317 req->setVirt(0, addr, dataSize, flags, thread->readPC());
318
319 // translate to physical address
320 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
321
322 // Now do the access.
323 if (fault == NoFault) {
324 Packet pkt = Packet(req,
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 308 unchanged lines hidden (view full) ---

317 req->setVirt(0, addr, dataSize, flags, thread->readPC());
318
319 // translate to physical address
320 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
321
322 // Now do the access.
323 if (fault == NoFault) {
324 Packet pkt = Packet(req,
325 req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
325 req->isLlsc() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
326 Packet::Broadcast);
327 pkt.dataStatic(dataPtr);
328
329 if (req->isMmapedIpr())
330 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
331 else {
332 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
333 dcache_latency += physmemPort.sendAtomic(&pkt);
334 else
335 dcache_latency += dcachePort.sendAtomic(&pkt);
336 }
337 dcache_access = true;
338
339 assert(!pkt.isError());
340
326 Packet::Broadcast);
327 pkt.dataStatic(dataPtr);
328
329 if (req->isMmapedIpr())
330 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
331 else {
332 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
333 dcache_latency += physmemPort.sendAtomic(&pkt);
334 else
335 dcache_latency += dcachePort.sendAtomic(&pkt);
336 }
337 dcache_access = true;
338
339 assert(!pkt.isError());
340
341 if (req->isLocked()) {
341 if (req->isLlsc()) {
342 TheISA::handleLockedRead(thread, req);
343 }
344 }
345
346 // This will need a new way to tell if it has a dcache attached.
347 if (req->isUncacheable())
348 recordEvent("Uncached Read");
349

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457 // translate to physical address
458 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write);
459
460 // Now do the access.
461 if (fault == NoFault) {
462 MemCmd cmd = MemCmd::WriteReq; // default
463 bool do_access = true; // flag to suppress cache access
464
342 TheISA::handleLockedRead(thread, req);
343 }
344 }
345
346 // This will need a new way to tell if it has a dcache attached.
347 if (req->isUncacheable())
348 recordEvent("Uncached Read");
349

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457 // translate to physical address
458 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write);
459
460 // Now do the access.
461 if (fault == NoFault) {
462 MemCmd cmd = MemCmd::WriteReq; // default
463 bool do_access = true; // flag to suppress cache access
464
465 if (req->isLocked()) {
465 if (req->isLlsc()) {
466 cmd = MemCmd::StoreCondReq;
467 do_access = TheISA::handleLockedWrite(thread, req);
468 } else if (req->isSwap()) {
469 cmd = MemCmd::SwapReq;
470 if (req->isCondSwap()) {
471 assert(res);
472 req->setExtraData(*res);
473 }

--- 249 unchanged lines hidden --- 		466 cmd = MemCmd::StoreCondReq;
467 do_access = TheISA::handleLockedWrite(thread, req);
468 } else if (req->isSwap()) {
469 cmd = MemCmd::SwapReq;
470 if (req->isCondSwap()) {
471 assert(res);
472 req->setExtraData(*res);
473 }

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