atomic.cc (5894:8091ac99341a) atomic.cc (5914:c92d57f579b1)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 593 unchanged lines hidden (view full) ---

602 if (!curStaticInst || !curStaticInst->isDelayedCommit())
603 checkForInterrupts();
604
605 checkPcEventQueue();
606
607 Fault fault = NoFault;
608
609 bool fromRom = isRomMicroPC(thread->readMicroPC());
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 593 unchanged lines hidden (view full) ---

602 if (!curStaticInst || !curStaticInst->isDelayedCommit())
603 checkForInterrupts();
604
605 checkPcEventQueue();
606
607 Fault fault = NoFault;
608
609 bool fromRom = isRomMicroPC(thread->readMicroPC());
610 if (!fromRom) {
610 if (!fromRom && !curMacroStaticInst) {
611 setupFetchRequest(&ifetch_req);
612 fault = thread->itb->translateAtomic(&ifetch_req, tc);
613 }
614
615 if (fault == NoFault) {
616 Tick icache_latency = 0;
617 bool icache_access = false;
618 dcache_access = false; // assume no dcache access
619
611 setupFetchRequest(&ifetch_req);
612 fault = thread->itb->translateAtomic(&ifetch_req, tc);
613 }
614
615 if (fault == NoFault) {
616 Tick icache_latency = 0;
617 bool icache_access = false;
618 dcache_access = false; // assume no dcache access
619
620 if (!fromRom) {
620 if (!fromRom && !curMacroStaticInst) {
621 // This is commented out because the predecoder would act like
622 // a tiny cache otherwise. It wouldn't be flushed when needed
623 // like the I cache. It should be flushed, and when that works
624 // this code should be uncommented.
625 //Fetch more instruction memory if necessary
626 //if(predecoder.needMoreBytes())
627 //{
628 icache_access = true;

--- 90 unchanged lines hidden --- 		621 // This is commented out because the predecoder would act like
622 // a tiny cache otherwise. It wouldn't be flushed when needed
623 // like the I cache. It should be flushed, and when that works
624 // this code should be uncommented.
625 //Fetch more instruction memory if necessary
626 //if(predecoder.needMoreBytes())
627 //{
628 icache_access = true;

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