atomic.cc (5606:6da7a58b0bc8) atomic.cc (5669:cbac62a59686)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 704 unchanged lines hidden (view full) ---

713 for (int i = 0; i < width; ++i) {
714 numCycles++;
715
716 if (!curStaticInst || !curStaticInst->isDelayedCommit())
717 checkForInterrupts();
718
719 checkPcEventQueue();
720
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 704 unchanged lines hidden (view full) ---

713 for (int i = 0; i < width; ++i) {
714 numCycles++;
715
716 if (!curStaticInst || !curStaticInst->isDelayedCommit())
717 checkForInterrupts();
718
719 checkPcEventQueue();
720
721 Fault fault = setupFetchRequest(&ifetch_req);
721 Fault fault = NoFault;
722
722
723 bool fromRom = isRomMicroPC(thread->readMicroPC());
724 if (!fromRom)
725 fault = setupFetchRequest(&ifetch_req);
726
723 if (fault == NoFault) {
724 Tick icache_latency = 0;
725 bool icache_access = false;
726 dcache_access = false; // assume no dcache access
727
727 if (fault == NoFault) {
728 Tick icache_latency = 0;
729 bool icache_access = false;
730 dcache_access = false; // assume no dcache access
731
728 //Fetch more instruction memory if necessary
729 //if(predecoder.needMoreBytes())
730 //{
731 icache_access = true;
732 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
733 Packet::Broadcast);
734 ifetch_pkt.dataStatic(&inst);
732 if (!fromRom) {
733 //Fetch more instruction memory if necessary
734 //if(predecoder.needMoreBytes())
735 //{
736 icache_access = true;
737 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
738 Packet::Broadcast);
739 ifetch_pkt.dataStatic(&inst);
735
740
736 if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
737 icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
738 else
739 icache_latency = icachePort.sendAtomic(&ifetch_pkt);
741 if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
742 icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
743 else
744 icache_latency = icachePort.sendAtomic(&ifetch_pkt);
740
745
741 assert(!ifetch_pkt.isError());
746 assert(!ifetch_pkt.isError());
742
747
743 // ifetch_req is initialized to read the instruction directly
744 // into the CPU object's inst field.
745 //}
748 // ifetch_req is initialized to read the instruction directly
749 // into the CPU object's inst field.
750 //}
751 }
746
747 preExecute();
748
749 if (curStaticInst) {
750 fault = curStaticInst->execute(this, traceData);
751
752 // keep an instruction count
753 if (fault == NoFault)

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753 preExecute();
754
755 if (curStaticInst) {
756 fault = curStaticInst->execute(this, traceData);
757
758 // keep an instruction count
759 if (fault == NoFault)

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