atomic.cc (5529:9ae69b9cd7fd) atomic.cc (5606:6da7a58b0bc8)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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38#include "mem/packet_access.hh"
39#include "params/AtomicSimpleCPU.hh"
40#include "sim/system.hh"
41
42using namespace std;
43using namespace TheISA;
44
45AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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38#include "mem/packet_access.hh"
39#include "params/AtomicSimpleCPU.hh"
40#include "sim/system.hh"
41
42using namespace std;
43using namespace TheISA;
44
45AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
46 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
46 : Event(CPU_Tick_Pri), cpu(c)
47{
48}
49
50
51void
52AtomicSimpleCPU::TickEvent::process()
53{
54 cpu->tick();

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196 if (_status == Idle || _status == SwitchedOut)
197 return;
198
199 DPRINTF(SimpleCPU, "Resume\n");
200 assert(system->getMemoryMode() == Enums::atomic);
201
202 changeState(SimObject::Running);
203 if (thread->status() == ThreadContext::Active) {
47{
48}
49
50
51void
52AtomicSimpleCPU::TickEvent::process()
53{
54 cpu->tick();

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196 if (_status == Idle || _status == SwitchedOut)
197 return;
198
199 DPRINTF(SimpleCPU, "Resume\n");
200 assert(system->getMemoryMode() == Enums::atomic);
201
202 changeState(SimObject::Running);
203 if (thread->status() == ThreadContext::Active) {
204 if (!tickEvent.scheduled()) {
205 tickEvent.schedule(nextCycle());
206 }
204 if (!tickEvent.scheduled())
205 schedule(tickEvent, nextCycle());
207 }
208}
209
210void
211AtomicSimpleCPU::switchOut()
212{
213 assert(_status == Running || _status == Idle);
214 _status = SwitchedOut;

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225 assert(!tickEvent.scheduled());
226
227 // if any of this CPU's ThreadContexts are active, mark the CPU as
228 // running and schedule its tick event.
229 for (int i = 0; i < threadContexts.size(); ++i) {
230 ThreadContext *tc = threadContexts[i];
231 if (tc->status() == ThreadContext::Active && _status != Running) {
232 _status = Running;
206 }
207}
208
209void
210AtomicSimpleCPU::switchOut()
211{
212 assert(_status == Running || _status == Idle);
213 _status = SwitchedOut;

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224 assert(!tickEvent.scheduled());
225
226 // if any of this CPU's ThreadContexts are active, mark the CPU as
227 // running and schedule its tick event.
228 for (int i = 0; i < threadContexts.size(); ++i) {
229 ThreadContext *tc = threadContexts[i];
230 if (tc->status() == ThreadContext::Active && _status != Running) {
231 _status = Running;
233 tickEvent.schedule(nextCycle());
232 schedule(tickEvent, nextCycle());
234 break;
235 }
236 }
237 if (_status != Running) {
238 _status = Idle;
239 }
240 assert(threadContexts.size() == 1);
241 cpuId = tc->readCpuId();

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255
256 assert(_status == Idle);
257 assert(!tickEvent.scheduled());
258
259 notIdleFraction++;
260 numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend);
261
262 //Make sure ticks are still on multiples of cycles
233 break;
234 }
235 }
236 if (_status != Running) {
237 _status = Idle;
238 }
239 assert(threadContexts.size() == 1);
240 cpuId = tc->readCpuId();

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254
255 assert(_status == Idle);
256 assert(!tickEvent.scheduled());
257
258 notIdleFraction++;
259 numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend);
260
261 //Make sure ticks are still on multiples of cycles
263 tickEvent.schedule(nextCycle(curTick + ticks(delay)));
262 schedule(tickEvent, nextCycle(curTick + ticks(delay)));
264 _status = Running;
265}
266
267
268void
269AtomicSimpleCPU::suspendContext(int thread_num)
270{
271 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
272
273 assert(thread_num == 0);
274 assert(thread);
275
276 assert(_status == Running);
277
278 // tick event may not be scheduled if this gets called from inside
279 // an instruction's execution, e.g. "quiesce"
280 if (tickEvent.scheduled())
263 _status = Running;
264}
265
266
267void
268AtomicSimpleCPU::suspendContext(int thread_num)
269{
270 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
271
272 assert(thread_num == 0);
273 assert(thread);
274
275 assert(_status == Running);
276
277 // tick event may not be scheduled if this gets called from inside
278 // an instruction's execution, e.g. "quiesce"
279 if (tickEvent.scheduled())
281 tickEvent.deschedule();
280 deschedule(tickEvent);
282
283 notIdleFraction--;
284 _status = Idle;
285}
286
287
288template <class T>
289Fault

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789 advancePC(fault);
790 }
791
792 // instruction takes at least one cycle
793 if (latency < ticks(1))
794 latency = ticks(1);
795
796 if (_status != Idle)
281
282 notIdleFraction--;
283 _status = Idle;
284}
285
286
287template <class T>
288Fault

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788 advancePC(fault);
789 }
790
791 // instruction takes at least one cycle
792 if (latency < ticks(1))
793 latency = ticks(1);
794
795 if (_status != Idle)
797 tickEvent.schedule(curTick + latency);
796 schedule(tickEvent, curTick + latency);
798}
799
800
801void
802AtomicSimpleCPU::printAddr(Addr a)
803{
804 dcachePort.printAddr(a);
805}

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798
799
800void
801AtomicSimpleCPU::printAddr(Addr a)
802{
803 dcachePort.printAddr(a);
804}

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