atomic.cc (5497:89a6483d7047) | atomic.cc (5529:9ae69b9cd7fd) |
---|---|
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 138 unchanged lines hidden (view full) --- 147 148#if FULL_SYSTEM 149 // Update the ThreadContext's memory ports (Functional/Virtual 150 // Ports) 151 cpu->tcBase()->connectMemPorts(cpu->tcBase()); 152#endif 153} 154 | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 138 unchanged lines hidden (view full) --- 147 148#if FULL_SYSTEM 149 // Update the ThreadContext's memory ports (Functional/Virtual 150 // Ports) 151 cpu->tcBase()->connectMemPorts(cpu->tcBase()); 152#endif 153} 154 |
155AtomicSimpleCPU::AtomicSimpleCPU(Params *p) | 155AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) |
156 : BaseSimpleCPU(p), tickEvent(this), width(p->width), 157 simulate_data_stalls(p->simulate_data_stalls), 158 simulate_inst_stalls(p->simulate_inst_stalls), 159 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this), 160 physmemPort(name() + "-iport", this), hasPhysMemPort(false) 161{ 162 _status = Idle; 163 --- 643 unchanged lines hidden (view full) --- 807 808//////////////////////////////////////////////////////////////////////// 809// 810// AtomicSimpleCPU Simulation Object 811// 812AtomicSimpleCPU * 813AtomicSimpleCPUParams::create() 814{ | 156 : BaseSimpleCPU(p), tickEvent(this), width(p->width), 157 simulate_data_stalls(p->simulate_data_stalls), 158 simulate_inst_stalls(p->simulate_inst_stalls), 159 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this), 160 physmemPort(name() + "-iport", this), hasPhysMemPort(false) 161{ 162 _status = Idle; 163 --- 643 unchanged lines hidden (view full) --- 807 808//////////////////////////////////////////////////////////////////////// 809// 810// AtomicSimpleCPU Simulation Object 811// 812AtomicSimpleCPU * 813AtomicSimpleCPUParams::create() 814{ |
815 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params(); 816 params->name = name; 817 params->numberOfThreads = 1; 818 params->max_insts_any_thread = max_insts_any_thread; 819 params->max_insts_all_threads = max_insts_all_threads; 820 params->max_loads_any_thread = max_loads_any_thread; 821 params->max_loads_all_threads = max_loads_all_threads; 822 params->progress_interval = progress_interval; 823 params->deferRegistration = defer_registration; 824 params->phase = phase; 825 params->clock = clock; 826 params->functionTrace = function_trace; 827 params->functionTraceStart = function_trace_start; 828 params->width = width; 829 params->simulate_data_stalls = simulate_data_stalls; 830 params->simulate_inst_stalls = simulate_inst_stalls; 831 params->system = system; 832 params->cpu_id = cpu_id; 833 params->tracer = tracer; 834 835 params->itb = itb; 836 params->dtb = dtb; 837#if FULL_SYSTEM 838 params->profile = profile; 839 params->do_quiesce = do_quiesce; 840 params->do_checkpoint_insts = do_checkpoint_insts; 841 params->do_statistics_insts = do_statistics_insts; 842#else | 815 numThreads = 1; 816#if !FULL_SYSTEM |
843 if (workload.size() != 1) 844 panic("only one workload allowed"); | 817 if (workload.size() != 1) 818 panic("only one workload allowed"); |
845 params->process = workload[0]; | |
846#endif | 819#endif |
847 848 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 849 return cpu; | 820 return new AtomicSimpleCPU(this); |
850} | 821} |