atomic.cc (5496:6899b894166f) atomic.cc (5497:89a6483d7047)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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143void
144AtomicSimpleCPU::DcachePort::setPeer(Port *port)
145{
146 Port::setPeer(port);
147
148#if FULL_SYSTEM
149 // Update the ThreadContext's memory ports (Functional/Virtual
150 // Ports)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 134 unchanged lines hidden (view full) ---

143void
144AtomicSimpleCPU::DcachePort::setPeer(Port *port)
145{
146 Port::setPeer(port);
147
148#if FULL_SYSTEM
149 // Update the ThreadContext's memory ports (Functional/Virtual
150 // Ports)
151 cpu->tcBase()->connectMemPorts();
151 cpu->tcBase()->connectMemPorts(cpu->tcBase());
152#endif
153}
154
155AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
156 : BaseSimpleCPU(p), tickEvent(this), width(p->width),
157 simulate_data_stalls(p->simulate_data_stalls),
158 simulate_inst_stalls(p->simulate_inst_stalls),
159 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),

--- 691 unchanged lines hidden --- 		152#endif
153}
154
155AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
156 : BaseSimpleCPU(p), tickEvent(this), width(p->width),
157 simulate_data_stalls(p->simulate_data_stalls),
158 simulate_inst_stalls(p->simulate_inst_stalls),
159 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),

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