atomic.cc (5408:703f1779cc89) atomic.cc (5487:f0ac4112e128)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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148#if FULL_SYSTEM
149 // Update the ThreadContext's memory ports (Functional/Virtual
150 // Ports)
151 cpu->tcBase()->connectMemPorts();
152#endif
153}
154
155AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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148#if FULL_SYSTEM
149 // Update the ThreadContext's memory ports (Functional/Virtual
150 // Ports)
151 cpu->tcBase()->connectMemPorts();
152#endif
153}
154
155AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
156 : BaseSimpleCPU(p), tickEvent(this),
157 width(p->width), simulate_stalls(p->simulate_stalls),
156 : BaseSimpleCPU(p), tickEvent(this), width(p->width),
157 simulate_data_stalls(p->simulate_data_stalls),
158 simulate_inst_stalls(p->simulate_inst_stalls),
158 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
159 physmemPort(name() + "-iport", this), hasPhysMemPort(false)
160{
161 _status = Idle;
162
163 icachePort.snoopRangeSent = false;
164 dcachePort.snoopRangeSent = false;
165

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706}
707
708
709void
710AtomicSimpleCPU::tick()
711{
712 DPRINTF(SimpleCPU, "Tick\n");
713
159 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
160 physmemPort(name() + "-iport", this), hasPhysMemPort(false)
161{
162 _status = Idle;
163
164 icachePort.snoopRangeSent = false;
165 dcachePort.snoopRangeSent = false;
166

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707}
708
709
710void
711AtomicSimpleCPU::tick()
712{
713 DPRINTF(SimpleCPU, "Tick\n");
714
714 Tick latency = ticks(1); // instruction takes one cycle by default
715 Tick latency = 0;
715
716 for (int i = 0; i < width; ++i) {
717 numCycles++;
718
719 if (!curStaticInst || !curStaticInst->isDelayedCommit())
720 checkForInterrupts();
721
722 checkPcEventQueue();

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764 postExecute();
765 }
766
767 // @todo remove me after debugging with legion done
768 if (curStaticInst && (!curStaticInst->isMicroop() ||
769 curStaticInst->isFirstMicroop()))
770 instCnt++;
771
716
717 for (int i = 0; i < width; ++i) {
718 numCycles++;
719
720 if (!curStaticInst || !curStaticInst->isDelayedCommit())
721 checkForInterrupts();
722
723 checkPcEventQueue();

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765 postExecute();
766 }
767
768 // @todo remove me after debugging with legion done
769 if (curStaticInst && (!curStaticInst->isMicroop() ||
770 curStaticInst->isFirstMicroop()))
771 instCnt++;
772
772 if (simulate_stalls) {
773 Tick icache_stall =
774 icache_access ? icache_latency - ticks(1) : 0;
775 Tick dcache_stall =
776 dcache_access ? dcache_latency - ticks(1) : 0;
777 Tick stall_cycles = (icache_stall + dcache_stall) / ticks(1);
778 if (ticks(stall_cycles) < (icache_stall + dcache_stall))
779 latency += ticks(stall_cycles+1);
780 else
781 latency += ticks(stall_cycles);
773 Tick stall_ticks = 0;
774 if (simulate_inst_stalls && icache_access)
775 stall_ticks += icache_latency;
776
777 if (simulate_data_stalls && dcache_access)
778 stall_ticks += dcache_latency;
779
780 if (stall_ticks) {
781 Tick stall_cycles = stall_ticks / ticks(1);
782 Tick aligned_stall_ticks = ticks(stall_cycles);
783
784 if (aligned_stall_ticks < stall_ticks)
785 aligned_stall_ticks += 1;
786
787 latency += aligned_stall_ticks;
782 }
783
784 }
785 if(fault != NoFault || !stayAtPC)
786 advancePC(fault);
787 }
788
788 }
789
790 }
791 if(fault != NoFault || !stayAtPC)
792 advancePC(fault);
793 }
794
795 // instruction takes at least one cycle
796 if (latency < ticks(1))
797 latency = ticks(1);
798
789 if (_status != Idle)
790 tickEvent.schedule(curTick + latency);
791}
792
793
794void
795AtomicSimpleCPU::printAddr(Addr a)
796{

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814 params->max_loads_all_threads = max_loads_all_threads;
815 params->progress_interval = progress_interval;
816 params->deferRegistration = defer_registration;
817 params->phase = phase;
818 params->clock = clock;
819 params->functionTrace = function_trace;
820 params->functionTraceStart = function_trace_start;
821 params->width = width;
799 if (_status != Idle)
800 tickEvent.schedule(curTick + latency);
801}
802
803
804void
805AtomicSimpleCPU::printAddr(Addr a)
806{

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824 params->max_loads_all_threads = max_loads_all_threads;
825 params->progress_interval = progress_interval;
826 params->deferRegistration = defer_registration;
827 params->phase = phase;
828 params->clock = clock;
829 params->functionTrace = function_trace;
830 params->functionTraceStart = function_trace_start;
831 params->width = width;
822 params->simulate_stalls = simulate_stalls;
832 params->simulate_data_stalls = simulate_data_stalls;
833 params->simulate_inst_stalls = simulate_inst_stalls;
823 params->system = system;
824 params->cpu_id = cpu_id;
825 params->tracer = tracer;
826
827 params->itb = itb;
828 params->dtb = dtb;
829#if FULL_SYSTEM
830 params->profile = profile;

--- 12 unchanged lines hidden --- 		834 params->system = system;
835 params->cpu_id = cpu_id;
836 params->tracer = tracer;
837
838 params->itb = itb;
839 params->dtb = dtb;
840#if FULL_SYSTEM
841 params->profile = profile;

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