atomic.cc (5336:c7e21f4e5a2e) atomic.cc (5348:7847a4bf9641)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 699 unchanged lines hidden (view full) ---

708 Tick latency = ticks(1); // instruction takes one cycle by default
709
710 for (int i = 0; i < width; ++i) {
711 numCycles++;
712
713 if (!curStaticInst || !curStaticInst->isDelayedCommit())
714 checkForInterrupts();
715
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 699 unchanged lines hidden (view full) ---

708 Tick latency = ticks(1); // instruction takes one cycle by default
709
710 for (int i = 0; i < width; ++i) {
711 numCycles++;
712
713 if (!curStaticInst || !curStaticInst->isDelayedCommit())
714 checkForInterrupts();
715
716 checkPcEventQueue();
717
716 Fault fault = setupFetchRequest(&ifetch_req);
717
718 if (fault == NoFault) {
719 Tick icache_latency = 0;
720 bool icache_access = false;
721 dcache_access = false; // assume no dcache access
722
723 //Fetch more instruction memory if necessary

--- 111 unchanged lines hidden --- 		718 Fault fault = setupFetchRequest(&ifetch_req);
719
720 if (fault == NoFault) {
721 Tick icache_latency = 0;
722 bool icache_access = false;
723 dcache_access = false; // assume no dcache access
724
725 //Fetch more instruction memory if necessary

--- 111 unchanged lines hidden ---