atomic.cc (5278:4c963dc4ab07) atomic.cc (5310:4164e6bfcc8a)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 65 unchanged lines hidden (view full) ---

74 else
75 panic("No Such Port\n");
76}
77
78void
79AtomicSimpleCPU::init()
80{
81 BaseCPU::init();
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 65 unchanged lines hidden (view full) ---

74 else
75 panic("No Such Port\n");
76}
77
78void
79AtomicSimpleCPU::init()
80{
81 BaseCPU::init();
82 cpuId = tc->readCpuId();
82#if FULL_SYSTEM
83 for (int i = 0; i < threadContexts.size(); ++i) {
84 ThreadContext *tc = threadContexts[i];
85
86 // initialize CPU, including PC
83#if FULL_SYSTEM
84 for (int i = 0; i < threadContexts.size(); ++i) {
85 ThreadContext *tc = threadContexts[i];
86
87 // initialize CPU, including PC
87 TheISA::initCPU(tc, tc->readCpuId());
88 TheISA::initCPU(tc, cpuId);
88 }
89#endif
90 if (hasPhysMemPort) {
91 bool snoop = false;
92 AddrRangeList pmAddrList;
93 physmemPort.getPeerAddressRanges(pmAddrList, snoop);
94 physMemAddr = *pmAddrList.begin();
95 }
89 }
90#endif
91 if (hasPhysMemPort) {
92 bool snoop = false;
93 AddrRangeList pmAddrList;
94 physmemPort.getPeerAddressRanges(pmAddrList, snoop);
95 physMemAddr = *pmAddrList.begin();
96 }
97 ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
98 data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
99 data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
96}
97
98bool
99AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
100{
101 panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
102 return true;
103}

--- 50 unchanged lines hidden (view full) ---

154 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
155 physmemPort(name() + "-iport", this), hasPhysMemPort(false)
156{
157 _status = Idle;
158
159 icachePort.snoopRangeSent = false;
160 dcachePort.snoopRangeSent = false;
161
100}
101
102bool
103AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
104{
105 panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
106 return true;
107}

--- 50 unchanged lines hidden (view full) ---

158 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
159 physmemPort(name() + "-iport", this), hasPhysMemPort(false)
160{
161 _status = Idle;
162
163 icachePort.snoopRangeSent = false;
164 dcachePort.snoopRangeSent = false;
165
162 ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
163 data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
164 data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
165}
166
167
168AtomicSimpleCPU::~AtomicSimpleCPU()
169{
170}
171
172void

--- 62 unchanged lines hidden (view full) ---

235 break;
236 }
237 }
238 if (_status != Running) {
239 _status = Idle;
240 }
241 assert(threadContexts.size() == 1);
242 cpuId = tc->readCpuId();
166}
167
168
169AtomicSimpleCPU::~AtomicSimpleCPU()
170{
171}
172
173void

--- 62 unchanged lines hidden (view full) ---

236 break;
237 }
238 }
239 if (_status != Running) {
240 _status = Idle;
241 }
242 assert(threadContexts.size() == 1);
243 cpuId = tc->readCpuId();
244 ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
245 data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
246 data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
243}
244
245
246void
247AtomicSimpleCPU::activateContext(int thread_num, int delay)
248{
249 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
250

--- 573 unchanged lines hidden --- 		247}
248
249
250void
251AtomicSimpleCPU::activateContext(int thread_num, int delay)
252{
253 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
254

--- 573 unchanged lines hidden ---