atomic.cc (4968:f1c856d8c460) atomic.cc (4986:b7c82ad6b3ef)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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306 dcache_latency = TheISA::handleIprRead(thread->getTC(), &pkt);
307 else {
308 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
309 dcache_latency = physmemPort.sendAtomic(&pkt);
310 else
311 dcache_latency = dcachePort.sendAtomic(&pkt);
312 }
313 dcache_access = true;
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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306 dcache_latency = TheISA::handleIprRead(thread->getTC(), &pkt);
307 else {
308 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
309 dcache_latency = physmemPort.sendAtomic(&pkt);
310 else
311 dcache_latency = dcachePort.sendAtomic(&pkt);
312 }
313 dcache_access = true;
314
314 assert(!pkt.isError());
315
316 data = gtoh(data);
317
318 if (req->isLocked()) {
319 TheISA::handleLockedRead(thread, req);
320 }
321 }

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531 Packet::Broadcast);
532 ifetch_pkt.dataStatic(&inst);
533
534 if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
535 icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
536 else
537 icache_latency = icachePort.sendAtomic(&ifetch_pkt);
538
315 assert(!pkt.isError());
316
317 data = gtoh(data);
318
319 if (req->isLocked()) {
320 TheISA::handleLockedRead(thread, req);
321 }
322 }

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532 Packet::Broadcast);
533 ifetch_pkt.dataStatic(&inst);
534
535 if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
536 icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
537 else
538 icache_latency = icachePort.sendAtomic(&ifetch_pkt);
539
540 assert(!ifetch_pkt.isError());
539
540 // ifetch_req is initialized to read the instruction directly
541 // into the CPU object's inst field.
542 //}
543
544 preExecute();
545
546 if(curStaticInst)

--- 74 unchanged lines hidden --- 		541
542 // ifetch_req is initialized to read the instruction directly
543 // into the CPU object's inst field.
544 //}
545
546 preExecute();
547
548 if(curStaticInst)

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