atomic.cc (4940:23874ae87540) atomic.cc (4968:f1c856d8c460)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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62
63Port *
64AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
65{
66 if (if_name == "dcache_port")
67 return &dcachePort;
68 else if (if_name == "icache_port")
69 return &icachePort;
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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62
63Port *
64AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
65{
66 if (if_name == "dcache_port")
67 return &dcachePort;
68 else if (if_name == "icache_port")
69 return &icachePort;
70 else if (if_name == "physmem_port") {
71 hasPhysMemPort = true;
72 return &physmemPort;
73 }
70 else
71 panic("No Such Port\n");
72}
73
74void
75AtomicSimpleCPU::init()
76{
77 BaseCPU::init();
78#if FULL_SYSTEM
79 for (int i = 0; i < threadContexts.size(); ++i) {
80 ThreadContext *tc = threadContexts[i];
81
82 // initialize CPU, including PC
83 TheISA::initCPU(tc, tc->readCpuId());
84 }
85#endif
74 else
75 panic("No Such Port\n");
76}
77
78void
79AtomicSimpleCPU::init()
80{
81 BaseCPU::init();
82#if FULL_SYSTEM
83 for (int i = 0; i < threadContexts.size(); ++i) {
84 ThreadContext *tc = threadContexts[i];
85
86 // initialize CPU, including PC
87 TheISA::initCPU(tc, tc->readCpuId());
88 }
89#endif
90 if (hasPhysMemPort) {
91 bool snoop = false;
92 AddrRangeList pmAddrList;
93 physmemPort.getPeerAddressRanges(pmAddrList, snoop);
94 physMemAddr = *pmAddrList.begin();
95 }
86}
87
88bool
89AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
90{
91 panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
92 return true;
93}

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136 // Ports)
137 cpu->tcBase()->connectMemPorts();
138#endif
139}
140
141AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
142 : BaseSimpleCPU(p), tickEvent(this),
143 width(p->width), simulate_stalls(p->simulate_stalls),
96}
97
98bool
99AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
100{
101 panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
102 return true;
103}

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146 // Ports)
147 cpu->tcBase()->connectMemPorts();
148#endif
149}
150
151AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
152 : BaseSimpleCPU(p), tickEvent(this),
153 width(p->width), simulate_stalls(p->simulate_stalls),
144 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
154 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
155 physmemPort(name() + "-iport", this), hasPhysMemPort(false)
145{
146 _status = Idle;
147
148 icachePort.snoopRangeSent = false;
149 dcachePort.snoopRangeSent = false;
150
151 ifetch_req.setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
152 data_read_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too

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288 Packet pkt =
289 Packet(req,
290 req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
291 Packet::Broadcast);
292 pkt.dataStatic(&data);
293
294 if (req->isMmapedIpr())
295 dcache_latency = TheISA::handleIprRead(thread->getTC(), &pkt);
156{
157 _status = Idle;
158
159 icachePort.snoopRangeSent = false;
160 dcachePort.snoopRangeSent = false;
161
162 ifetch_req.setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
163 data_read_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too

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299 Packet pkt =
300 Packet(req,
301 req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
302 Packet::Broadcast);
303 pkt.dataStatic(&data);
304
305 if (req->isMmapedIpr())
306 dcache_latency = TheISA::handleIprRead(thread->getTC(), &pkt);
296 else
297 dcache_latency = dcachePort.sendAtomic(&pkt);
307 else {
308 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
309 dcache_latency = physmemPort.sendAtomic(&pkt);
310 else
311 dcache_latency = dcachePort.sendAtomic(&pkt);
312 }
298 dcache_access = true;
299 assert(!pkt.isError());
300
301 data = gtoh(data);
302
303 if (req->isLocked()) {
304 TheISA::handleLockedRead(thread, req);
305 }

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397 if (do_access) {
398 Packet pkt = Packet(req, cmd, Packet::Broadcast);
399 pkt.dataStatic(&data);
400
401 if (req->isMmapedIpr()) {
402 dcache_latency = TheISA::handleIprWrite(thread->getTC(), &pkt);
403 } else {
404 data = htog(data);
313 dcache_access = true;
314 assert(!pkt.isError());
315
316 data = gtoh(data);
317
318 if (req->isLocked()) {
319 TheISA::handleLockedRead(thread, req);
320 }

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412 if (do_access) {
413 Packet pkt = Packet(req, cmd, Packet::Broadcast);
414 pkt.dataStatic(&data);
415
416 if (req->isMmapedIpr()) {
417 dcache_latency = TheISA::handleIprWrite(thread->getTC(), &pkt);
418 } else {
419 data = htog(data);
405 dcache_latency = dcachePort.sendAtomic(&pkt);
420 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
421 dcache_latency = physmemPort.sendAtomic(&pkt);
422 else
423 dcache_latency = dcachePort.sendAtomic(&pkt);
406 }
407 dcache_access = true;
408 assert(!pkt.isError());
409
410 if (req->isSwap()) {
411 assert(res);
412 *res = pkt.get<T>();
413 }

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508 //Fetch more instruction memory if necessary
509 //if(predecoder.needMoreBytes())
510 //{
511 icache_access = true;
512 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
513 Packet::Broadcast);
514 ifetch_pkt.dataStatic(&inst);
515
424 }
425 dcache_access = true;
426 assert(!pkt.isError());
427
428 if (req->isSwap()) {
429 assert(res);
430 *res = pkt.get<T>();
431 }

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526 //Fetch more instruction memory if necessary
527 //if(predecoder.needMoreBytes())
528 //{
529 icache_access = true;
530 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
531 Packet::Broadcast);
532 ifetch_pkt.dataStatic(&inst);
533
516 icache_latency = icachePort.sendAtomic(&ifetch_pkt);
534 if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
535 icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
536 else
537 icache_latency = icachePort.sendAtomic(&ifetch_pkt);
538
539
517 // ifetch_req is initialized to read the instruction directly
518 // into the CPU object's inst field.
519 //}
520
521 preExecute();
522
523 if(curStaticInst)
524 {

--- 73 unchanged lines hidden --- 		540 // ifetch_req is initialized to read the instruction directly
541 // into the CPU object's inst field.
542 //}
543
544 preExecute();
545
546 if(curStaticInst)
547 {

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