atomic.cc (4878:5b747482d2d8) atomic.cc (4918:3214e3694fb2)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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31#include "arch/locked_mem.hh"
32#include "arch/mmaped_ipr.hh"
33#include "arch/utility.hh"
34#include "base/bigint.hh"
35#include "cpu/exetrace.hh"
36#include "cpu/simple/atomic.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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31#include "arch/locked_mem.hh"
32#include "arch/mmaped_ipr.hh"
33#include "arch/utility.hh"
34#include "base/bigint.hh"
35#include "cpu/exetrace.hh"
36#include "cpu/simple/atomic.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "sim/builder.hh"
39#include "params/AtomicSimpleCPU.hh"
40#include "sim/system.hh"
41
42using namespace std;
43using namespace TheISA;
44
45AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
46 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
47{

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179 BaseSimpleCPU::unserialize(cp, section);
180 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
181}
182
183void
184AtomicSimpleCPU::resume()
185{
186 if (_status != SwitchedOut && _status != Idle) {
40#include "sim/system.hh"
41
42using namespace std;
43using namespace TheISA;
44
45AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
46 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
47{

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179 BaseSimpleCPU::unserialize(cp, section);
180 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
181}
182
183void
184AtomicSimpleCPU::resume()
185{
186 if (_status != SwitchedOut && _status != Idle) {
187 assert(system->getMemoryMode() == System::Atomic);
187 assert(system->getMemoryMode() == Enums::atomic);
188
189 changeState(SimObject::Running);
190 if (thread->status() == ThreadContext::Active) {
191 if (!tickEvent.scheduled()) {
192 tickEvent.schedule(nextCycle());
193 }
194 }
195 }

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543 tickEvent.schedule(curTick + latency);
544}
545
546
547////////////////////////////////////////////////////////////////////////
548//
549// AtomicSimpleCPU Simulation Object
550//
188
189 changeState(SimObject::Running);
190 if (thread->status() == ThreadContext::Active) {
191 if (!tickEvent.scheduled()) {
192 tickEvent.schedule(nextCycle());
193 }
194 }
195 }

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543 tickEvent.schedule(curTick + latency);
544}
545
546
547////////////////////////////////////////////////////////////////////////
548//
549// AtomicSimpleCPU Simulation Object
550//
551BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
552
553 Param<Counter> max_insts_any_thread;
554 Param<Counter> max_insts_all_threads;
555 Param<Counter> max_loads_any_thread;
556 Param<Counter> max_loads_all_threads;
557 Param<Tick> progress_interval;
558 SimObjectParam<System *> system;
559 Param<int> cpu_id;
560
561#if FULL_SYSTEM
562 SimObjectParam<TheISA::ITB *> itb;
563 SimObjectParam<TheISA::DTB *> dtb;
564 Param<Tick> profile;
565
566 Param<bool> do_quiesce;
567 Param<bool> do_checkpoint_insts;
568 Param<bool> do_statistics_insts;
569#else
570 SimObjectParam<Process *> workload;
571#endif // FULL_SYSTEM
572
573 Param<int> clock;
574 Param<int> phase;
575
576 Param<bool> defer_registration;
577 Param<int> width;
578 Param<bool> function_trace;
579 Param<Tick> function_trace_start;
580 Param<bool> simulate_stalls;
581
582END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
583
584BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
585
586 INIT_PARAM(max_insts_any_thread,
587 "terminate when any thread reaches this inst count"),
588 INIT_PARAM(max_insts_all_threads,
589 "terminate when all threads have reached this inst count"),
590 INIT_PARAM(max_loads_any_thread,
591 "terminate when any thread reaches this load count"),
592 INIT_PARAM(max_loads_all_threads,
593 "terminate when all threads have reached this load count"),
594 INIT_PARAM(progress_interval, "Progress interval"),
595 INIT_PARAM(system, "system object"),
596 INIT_PARAM(cpu_id, "processor ID"),
597
598#if FULL_SYSTEM
599 INIT_PARAM(itb, "Instruction TLB"),
600 INIT_PARAM(dtb, "Data TLB"),
601 INIT_PARAM(profile, ""),
602 INIT_PARAM(do_quiesce, ""),
603 INIT_PARAM(do_checkpoint_insts, ""),
604 INIT_PARAM(do_statistics_insts, ""),
605#else
606 INIT_PARAM(workload, "processes to run"),
607#endif // FULL_SYSTEM
608
609 INIT_PARAM(clock, "clock speed"),
610 INIT_PARAM_DFLT(phase, "clock phase", 0),
611 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
612 INIT_PARAM(width, "cpu width"),
613 INIT_PARAM(function_trace, "Enable function trace"),
614 INIT_PARAM(function_trace_start, "Cycle to start function trace"),
615 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
616
617END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
618
619
620CREATE_SIM_OBJECT(AtomicSimpleCPU)
551AtomicSimpleCPU *
552AtomicSimpleCPUParams::create()
621{
622 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
553{
554 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
623 params->name = getInstanceName();
555 params->name = name;
624 params->numberOfThreads = 1;
625 params->max_insts_any_thread = max_insts_any_thread;
626 params->max_insts_all_threads = max_insts_all_threads;
627 params->max_loads_any_thread = max_loads_any_thread;
628 params->max_loads_all_threads = max_loads_all_threads;
629 params->progress_interval = progress_interval;
630 params->deferRegistration = defer_registration;
631 params->phase = phase;

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640#if FULL_SYSTEM
641 params->itb = itb;
642 params->dtb = dtb;
643 params->profile = profile;
644 params->do_quiesce = do_quiesce;
645 params->do_checkpoint_insts = do_checkpoint_insts;
646 params->do_statistics_insts = do_statistics_insts;
647#else
556 params->numberOfThreads = 1;
557 params->max_insts_any_thread = max_insts_any_thread;
558 params->max_insts_all_threads = max_insts_all_threads;
559 params->max_loads_any_thread = max_loads_any_thread;
560 params->max_loads_all_threads = max_loads_all_threads;
561 params->progress_interval = progress_interval;
562 params->deferRegistration = defer_registration;
563 params->phase = phase;

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572#if FULL_SYSTEM
573 params->itb = itb;
574 params->dtb = dtb;
575 params->profile = profile;
576 params->do_quiesce = do_quiesce;
577 params->do_checkpoint_insts = do_checkpoint_insts;
578 params->do_statistics_insts = do_statistics_insts;
579#else
648 params->process = workload;
580 if (workload.size() != 1)
581 panic("only one workload allowed");
582 params->process = workload[0];
649#endif
650
651 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
652 return cpu;
653}
583#endif
584
585 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
586 return cpu;
587}
654
655REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
656