atomic.cc (4873:b135f6e6adfe) atomic.cc (4878:5b747482d2d8)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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275 traceData->setAddr(addr);
276 }
277
278 // translate to physical address
279 Fault fault = thread->translateDataReadReq(req);
280
281 // Now do the access.
282 if (fault == NoFault) {
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 266 unchanged lines hidden (view full) ---

275 traceData->setAddr(addr);
276 }
277
278 // translate to physical address
279 Fault fault = thread->translateDataReadReq(req);
280
281 // Now do the access.
282 if (fault == NoFault) {
283 Packet pkt = Packet(req, MemCmd::ReadReq, Packet::Broadcast);
283 Packet pkt =
284 Packet(req,
285 req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
286 Packet::Broadcast);
284 pkt.dataStatic(&data);
285
286 if (req->isMmapedIpr())
287 dcache_latency = TheISA::handleIprRead(thread->getTC(), &pkt);
288 else
289 dcache_latency = dcachePort.sendAtomic(&pkt);
290 dcache_access = true;
291 assert(!pkt.isError());

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365 traceData->setAddr(addr);
366 }
367
368 // translate to physical address
369 Fault fault = thread->translateDataWriteReq(req);
370
371 // Now do the access.
372 if (fault == NoFault) {
287 pkt.dataStatic(&data);
288
289 if (req->isMmapedIpr())
290 dcache_latency = TheISA::handleIprRead(thread->getTC(), &pkt);
291 else
292 dcache_latency = dcachePort.sendAtomic(&pkt);
293 dcache_access = true;
294 assert(!pkt.isError());

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368 traceData->setAddr(addr);
369 }
370
371 // translate to physical address
372 Fault fault = thread->translateDataWriteReq(req);
373
374 // Now do the access.
375 if (fault == NoFault) {
373 Packet pkt =
374 Packet(req, req->isSwap() ? MemCmd::SwapReq : MemCmd::WriteReq,
375 Packet::Broadcast);
376 pkt.dataStatic(&data);
377
376 MemCmd cmd = MemCmd::WriteReq; // default
378 bool do_access = true; // flag to suppress cache access
379
380 if (req->isLocked()) {
377 bool do_access = true; // flag to suppress cache access
378
379 if (req->isLocked()) {
380 cmd = MemCmd::StoreCondReq;
381 do_access = TheISA::handleLockedWrite(thread, req);
381 do_access = TheISA::handleLockedWrite(thread, req);
382 } else if (req->isSwap()) {
383 cmd = MemCmd::SwapReq;
384 if (req->isCondSwap()) {
385 assert(res);
386 req->setExtraData(*res);
387 }
382 }
388 }
383 if (req->isCondSwap()) {
384 assert(res);
385 req->setExtraData(*res);
386 }
387
389
388
389 if (do_access) {
390 if (do_access) {
391 Packet pkt = Packet(req, cmd, Packet::Broadcast);
392 pkt.dataStatic(&data);
393
390 if (req->isMmapedIpr()) {
391 dcache_latency = TheISA::handleIprWrite(thread->getTC(), &pkt);
392 } else {
393 data = htog(data);
394 dcache_latency = dcachePort.sendAtomic(&pkt);
395 }
396 dcache_access = true;
397 assert(!pkt.isError());
394 if (req->isMmapedIpr()) {
395 dcache_latency = TheISA::handleIprWrite(thread->getTC(), &pkt);
396 } else {
397 data = htog(data);
398 dcache_latency = dcachePort.sendAtomic(&pkt);
399 }
400 dcache_access = true;
401 assert(!pkt.isError());
402
403 if (req->isSwap()) {
404 assert(res);
405 *res = pkt.get<T>();
406 }
398 }
399
407 }
408
400 if (req->isSwap()) {
401 assert(res);
402 *res = pkt.get<T>();
403 } else if (res) {
409 if (res && !req->isSwap()) {
404 *res = req->getExtraData();
405 }
406 }
407
408 // This will need a new way to tell if it's hooked up to a cache or not.
409 if (req->isUncacheable())
410 recordEvent("Uncached Write");
411

--- 239 unchanged lines hidden --- 		410 *res = req->getExtraData();
411 }
412 }
413
414 // This will need a new way to tell if it's hooked up to a cache or not.
415 if (req->isUncacheable())
416 recordEvent("Uncached Write");
417

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