atomic.cc (4224:7e828583f2cb) atomic.cc (4240:cde9d7751cce)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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511 numCycles++;
512
513 if (!curStaticInst || !curStaticInst->isDelayedCommit())
514 checkForInterrupts();
515
516 Fault fault = setupFetchRequest(ifetch_req);
517
518 if (fault == NoFault) {
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 502 unchanged lines hidden (view full) ---

511 numCycles++;
512
513 if (!curStaticInst || !curStaticInst->isDelayedCommit())
514 checkForInterrupts();
515
516 Fault fault = setupFetchRequest(ifetch_req);
517
518 if (fault == NoFault) {
519 ifetch_pkt->reinitFromRequest();
519 Tick icache_latency = 0;
520 bool icache_access = false;
521 dcache_access = false; // assume no dcache access
520
522
521 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
522 // ifetch_req is initialized to read the instruction directly
523 // into the CPU object's inst field.
523 //Fetch more instruction memory if necessary
524 if(predecoder.needMoreBytes())
525 {
526 icache_access = true;
527 ifetch_pkt->reinitFromRequest();
524
528
525 dcache_access = false; // assume no dcache access
529 icache_latency = icachePort.sendAtomic(ifetch_pkt);
530 // ifetch_req is initialized to read the instruction directly
531 // into the CPU object's inst field.
532 }
533
526 preExecute();
527
534 preExecute();
535
528 fault = curStaticInst->execute(this, traceData);
529 postExecute();
536 if(curStaticInst)
537 {
538 fault = curStaticInst->execute(this, traceData);
539 postExecute();
540 }
530
531 // @todo remove me after debugging with legion done
532 if (curStaticInst && (!curStaticInst->isMicroOp() ||
533 curStaticInst->isFirstMicroOp()))
534 instCnt++;
535
536 if (simulate_stalls) {
541
542 // @todo remove me after debugging with legion done
543 if (curStaticInst && (!curStaticInst->isMicroOp() ||
544 curStaticInst->isFirstMicroOp()))
545 instCnt++;
546
547 if (simulate_stalls) {
537 Tick icache_stall = icache_latency - cycles(1);
548 Tick icache_stall =
549 icache_access ? icache_latency - cycles(1) : 0;
538 Tick dcache_stall =
539 dcache_access ? dcache_latency - cycles(1) : 0;
540 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
541 if (cycles(stall_cycles) < (icache_stall + dcache_stall))
542 latency += cycles(stall_cycles+1);
543 else
544 latency += cycles(stall_cycles);
545 }
546
547 }
550 Tick dcache_stall =
551 dcache_access ? dcache_latency - cycles(1) : 0;
552 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
553 if (cycles(stall_cycles) < (icache_stall + dcache_stall))
554 latency += cycles(stall_cycles+1);
555 else
556 latency += cycles(stall_cycles);
557 }
558
559 }
548
549 advancePC(fault);
560 if(predecoder.needMoreBytes())
561 advancePC(fault);
550 }
551
552 if (_status != Idle)
553 tickEvent.schedule(curTick + latency);
554}
555
556
557////////////////////////////////////////////////////////////////////////

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563
564 if (_status != Idle)
565 tickEvent.schedule(curTick + latency);
566}
567
568
569////////////////////////////////////////////////////////////////////////

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