atomic.cc (3807:1455bc719432) atomic.cc (3814:33bd4ec9d66a)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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290 if (fault == NoFault) {
291 pkt->reinitFromRequest();
292
293 if (req->isMmapedIpr())
294 dcache_latency = TheISA::handleIprRead(thread->getTC(),pkt);
295 else
296 dcache_latency = dcachePort.sendAtomic(pkt);
297 dcache_access = true;
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 281 unchanged lines hidden (view full) ---

290 if (fault == NoFault) {
291 pkt->reinitFromRequest();
292
293 if (req->isMmapedIpr())
294 dcache_latency = TheISA::handleIprRead(thread->getTC(),pkt);
295 else
296 dcache_latency = dcachePort.sendAtomic(pkt);
297 dcache_access = true;
298
299 assert(pkt->result == Packet::Success);
298#if !defined(NDEBUG)
299 if (pkt->result != Packet::Success)
300 panic("Unable to find responder for address pa = %#X va = %#X\n",
301 pkt->req->getPaddr(), pkt->req->getVaddr());
302#endif
300 data = pkt->get<T>();
301
302 if (req->isLocked()) {
303 TheISA::handleLockedRead(thread, req);
304 }
305 }
306
307 // This will need a new way to tell if it has a dcache attached.

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386 if (req->isMmapedIpr()) {
387 dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt);
388 } else {
389 data = htog(data);
390 dcache_latency = dcachePort.sendAtomic(pkt);
391 }
392 dcache_access = true;
393
303 data = pkt->get<T>();
304
305 if (req->isLocked()) {
306 TheISA::handleLockedRead(thread, req);
307 }
308 }
309
310 // This will need a new way to tell if it has a dcache attached.

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389 if (req->isMmapedIpr()) {
390 dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt);
391 } else {
392 data = htog(data);
393 dcache_latency = dcachePort.sendAtomic(pkt);
394 }
395 dcache_access = true;
396
394 assert(pkt->result == Packet::Success);
397#if !defined(NDEBUG)
398 if (pkt->result != Packet::Success)
399 panic("Unable to find responder for address pa = %#X va = %#X\n",
400 pkt->req->getPaddr(), pkt->req->getVaddr());
401#endif
395 }
396
397 if (req->isLocked()) {
398 uint64_t scResult = req->getScResult();
399 if (scResult != 0) {
400 // clear failure counter
401 thread->setStCondFailures(0);
402 }

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479 ifetch_pkt->reinitFromRequest();
480
481 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
482 // ifetch_req is initialized to read the instruction directly
483 // into the CPU object's inst field.
484
485 dcache_access = false; // assume no dcache access
486 preExecute();
402 }
403
404 if (req->isLocked()) {
405 uint64_t scResult = req->getScResult();
406 if (scResult != 0) {
407 // clear failure counter
408 thread->setStCondFailures(0);
409 }

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486 ifetch_pkt->reinitFromRequest();
487
488 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
489 // ifetch_req is initialized to read the instruction directly
490 // into the CPU object's inst field.
491
492 dcache_access = false; // assume no dcache access
493 preExecute();
494
487 fault = curStaticInst->execute(this, traceData);
488 postExecute();
489
495 fault = curStaticInst->execute(this, traceData);
496 postExecute();
497
498 // @todo remove me after debugging with legion done
499 if (curStaticInst && (!curStaticInst->isMicroOp() ||
500 curStaticInst->isLastMicroOp()))
501 instCnt++;
502
490 if (simulate_stalls) {
491 Tick icache_stall = icache_latency - cycles(1);
492 Tick dcache_stall =
493 dcache_access ? dcache_latency - cycles(1) : 0;
494 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
495 if (cycles(stall_cycles) < (icache_stall + dcache_stall))
496 latency += cycles(stall_cycles+1);
497 else

--- 123 unchanged lines hidden --- 		503 if (simulate_stalls) {
504 Tick icache_stall = icache_latency - cycles(1);
505 Tick dcache_stall =
506 dcache_access ? dcache_latency - cycles(1) : 0;
507 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
508 if (cycles(stall_cycles) < (icache_stall + dcache_stall))
509 latency += cycles(stall_cycles+1);
510 else

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