atomic.cc (3635:8f3b67d2accd) atomic.cc (3647:8121d4503cbc)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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102{
103 //No internal storage to update, just return
104 return;
105}
106
107void
108AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
109{
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 93 unchanged lines hidden (view full) ---

102{
103 //No internal storage to update, just return
104 return;
105}
106
107void
108AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
109{
110 if (status == RangeChange)
110 if (status == RangeChange) {
111 if (!snoopRangeSent) {
112 snoopRangeSent = true;
113 sendStatusChange(Port::RangeChange);
114 }
111 return;
115 return;
116 }
112
113 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
114}
115
116void
117AtomicSimpleCPU::CpuPort::recvRetry()
118{
119 panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
120}
121
122
123AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
124 : BaseSimpleCPU(p), tickEvent(this),
125 width(p->width), simulate_stalls(p->simulate_stalls),
126 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
127{
128 _status = Idle;
129
117
118 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
119}
120
121void
122AtomicSimpleCPU::CpuPort::recvRetry()
123{
124 panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
125}
126
127
128AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
129 : BaseSimpleCPU(p), tickEvent(this),
130 width(p->width), simulate_stalls(p->simulate_stalls),
131 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
132{
133 _status = Idle;
134
135 icachePort.snoopRangeSent = false;
136 dcachePort.snoopRangeSent = false;
137
130 ifetch_req = new Request();
131 ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
132 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
133 ifetch_pkt->dataStatic(&inst);
134
135 data_read_req = new Request();
136 data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
137 data_read_pkt = new Packet(data_read_req, Packet::ReadReq,

--- 457 unchanged lines hidden --- 		138 ifetch_req = new Request();
139 ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
140 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
141 ifetch_pkt->dataStatic(&inst);
142
143 data_read_req = new Request();
144 data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
145 data_read_pkt = new Packet(data_read_req, Packet::ReadReq,

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