atomic.cc (3402:db60546818d0) | atomic.cc (3430:5afdd6d7df69) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 58 unchanged lines hidden (view full) --- 67 return &icachePort; 68 else 69 panic("No Such Port\n"); 70} 71 72void 73AtomicSimpleCPU::init() 74{ | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 58 unchanged lines hidden (view full) --- 67 return &icachePort; 68 else 69 panic("No Such Port\n"); 70} 71 72void 73AtomicSimpleCPU::init() 74{ |
75 //Create Memory Ports (conect them up) 76// Port *mem_dport = mem->getPort(""); 77// dcachePort.setPeer(mem_dport); 78// mem_dport->setPeer(&dcachePort); 79 80// Port *mem_iport = mem->getPort(""); 81// icachePort.setPeer(mem_iport); 82// mem_iport->setPeer(&icachePort); 83 |
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75 BaseCPU::init(); 76#if FULL_SYSTEM 77 for (int i = 0; i < threadContexts.size(); ++i) { 78 ThreadContext *tc = threadContexts[i]; 79 80 // initialize CPU, including PC 81 TheISA::initCPU(tc, tc->readCpuId()); 82 } --- 137 unchanged lines hidden (view full) --- 220{ 221 assert(thread_num == 0); 222 assert(thread); 223 224 assert(_status == Idle); 225 assert(!tickEvent.scheduled()); 226 227 notIdleFraction++; | 84 BaseCPU::init(); 85#if FULL_SYSTEM 86 for (int i = 0; i < threadContexts.size(); ++i) { 87 ThreadContext *tc = threadContexts[i]; 88 89 // initialize CPU, including PC 90 TheISA::initCPU(tc, tc->readCpuId()); 91 } --- 137 unchanged lines hidden (view full) --- 229{ 230 assert(thread_num == 0); 231 assert(thread); 232 233 assert(_status == Idle); 234 assert(!tickEvent.scheduled()); 235 236 notIdleFraction++; |
237 //Make sure ticks are still on multiples of cycles 238 Tick nextTick = curTick + cycles(1) - 1; 239 nextTick -= (nextTick % (cycles(1))); |
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228 tickEvent.schedule(curTick + cycles(delay)); 229 _status = Running; 230} 231 232 233void 234AtomicSimpleCPU::suspendContext(int thread_num) 235{ --- 250 unchanged lines hidden (view full) --- 486// 487BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 488 489 Param<Counter> max_insts_any_thread; 490 Param<Counter> max_insts_all_threads; 491 Param<Counter> max_loads_any_thread; 492 Param<Counter> max_loads_all_threads; 493 Param<Tick> progress_interval; | 240 tickEvent.schedule(curTick + cycles(delay)); 241 _status = Running; 242} 243 244 245void 246AtomicSimpleCPU::suspendContext(int thread_num) 247{ --- 250 unchanged lines hidden (view full) --- 498// 499BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 500 501 Param<Counter> max_insts_any_thread; 502 Param<Counter> max_insts_all_threads; 503 Param<Counter> max_loads_any_thread; 504 Param<Counter> max_loads_all_threads; 505 Param<Tick> progress_interval; |
506 SimObjectParam<MemObject *> mem; |
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494 SimObjectParam<System *> system; 495 Param<int> cpu_id; 496 497#if FULL_SYSTEM 498 SimObjectParam<AlphaITB *> itb; 499 SimObjectParam<AlphaDTB *> dtb; 500 Param<Tick> profile; 501#else --- 16 unchanged lines hidden (view full) --- 518 "terminate when any thread reaches this inst count"), 519 INIT_PARAM(max_insts_all_threads, 520 "terminate when all threads have reached this inst count"), 521 INIT_PARAM(max_loads_any_thread, 522 "terminate when any thread reaches this load count"), 523 INIT_PARAM(max_loads_all_threads, 524 "terminate when all threads have reached this load count"), 525 INIT_PARAM(progress_interval, "Progress interval"), | 507 SimObjectParam<System *> system; 508 Param<int> cpu_id; 509 510#if FULL_SYSTEM 511 SimObjectParam<AlphaITB *> itb; 512 SimObjectParam<AlphaDTB *> dtb; 513 Param<Tick> profile; 514#else --- 16 unchanged lines hidden (view full) --- 531 "terminate when any thread reaches this inst count"), 532 INIT_PARAM(max_insts_all_threads, 533 "terminate when all threads have reached this inst count"), 534 INIT_PARAM(max_loads_any_thread, 535 "terminate when any thread reaches this load count"), 536 INIT_PARAM(max_loads_all_threads, 537 "terminate when all threads have reached this load count"), 538 INIT_PARAM(progress_interval, "Progress interval"), |
539 INIT_PARAM(mem, "memory"), |
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526 INIT_PARAM(system, "system object"), 527 INIT_PARAM(cpu_id, "processor ID"), 528 529#if FULL_SYSTEM 530 INIT_PARAM(itb, "Instruction TLB"), 531 INIT_PARAM(dtb, "Data TLB"), 532 INIT_PARAM(profile, ""), 533#else --- 21 unchanged lines hidden (view full) --- 555 params->max_loads_all_threads = max_loads_all_threads; 556 params->progress_interval = progress_interval; 557 params->deferRegistration = defer_registration; 558 params->clock = clock; 559 params->functionTrace = function_trace; 560 params->functionTraceStart = function_trace_start; 561 params->width = width; 562 params->simulate_stalls = simulate_stalls; | 540 INIT_PARAM(system, "system object"), 541 INIT_PARAM(cpu_id, "processor ID"), 542 543#if FULL_SYSTEM 544 INIT_PARAM(itb, "Instruction TLB"), 545 INIT_PARAM(dtb, "Data TLB"), 546 INIT_PARAM(profile, ""), 547#else --- 21 unchanged lines hidden (view full) --- 569 params->max_loads_all_threads = max_loads_all_threads; 570 params->progress_interval = progress_interval; 571 params->deferRegistration = defer_registration; 572 params->clock = clock; 573 params->functionTrace = function_trace; 574 params->functionTraceStart = function_trace_start; 575 params->width = width; 576 params->simulate_stalls = simulate_stalls; |
577 params->mem = mem; |
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563 params->system = system; 564 params->cpu_id = cpu_id; 565 566#if FULL_SYSTEM 567 params->itb = itb; 568 params->dtb = dtb; 569 params->profile = profile; 570#else 571 params->process = workload; 572#endif 573 574 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 575 return cpu; 576} 577 578REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU) 579 | 578 params->system = system; 579 params->cpu_id = cpu_id; 580 581#if FULL_SYSTEM 582 params->itb = itb; 583 params->dtb = dtb; 584 params->profile = profile; 585#else 586 params->process = workload; 587#endif 588 589 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 590 return cpu; 591} 592 593REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU) 594 |