atomic.cc (3393:43e1a001a7ce) | atomic.cc (3402:db60546818d0) |
---|---|
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 58 unchanged lines hidden (view full) --- 67 return &icachePort; 68 else 69 panic("No Such Port\n"); 70} 71 72void 73AtomicSimpleCPU::init() 74{ | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 58 unchanged lines hidden (view full) --- 67 return &icachePort; 68 else 69 panic("No Such Port\n"); 70} 71 72void 73AtomicSimpleCPU::init() 74{ |
75 //Create Memory Ports (conect them up) 76// Port *mem_dport = mem->getPort(""); 77// dcachePort.setPeer(mem_dport); 78// mem_dport->setPeer(&dcachePort); 79 80// Port *mem_iport = mem->getPort(""); 81// icachePort.setPeer(mem_iport); 82// mem_iport->setPeer(&icachePort); 83 | |
84 BaseCPU::init(); 85#if FULL_SYSTEM 86 for (int i = 0; i < threadContexts.size(); ++i) { 87 ThreadContext *tc = threadContexts[i]; 88 89 // initialize CPU, including PC 90 TheISA::initCPU(tc, tc->readCpuId()); 91 } --- 403 unchanged lines hidden (view full) --- 495// 496BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 497 498 Param<Counter> max_insts_any_thread; 499 Param<Counter> max_insts_all_threads; 500 Param<Counter> max_loads_any_thread; 501 Param<Counter> max_loads_all_threads; 502 Param<Tick> progress_interval; | 75 BaseCPU::init(); 76#if FULL_SYSTEM 77 for (int i = 0; i < threadContexts.size(); ++i) { 78 ThreadContext *tc = threadContexts[i]; 79 80 // initialize CPU, including PC 81 TheISA::initCPU(tc, tc->readCpuId()); 82 } --- 403 unchanged lines hidden (view full) --- 486// 487BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 488 489 Param<Counter> max_insts_any_thread; 490 Param<Counter> max_insts_all_threads; 491 Param<Counter> max_loads_any_thread; 492 Param<Counter> max_loads_all_threads; 493 Param<Tick> progress_interval; |
503 SimObjectParam<MemObject *> mem; | |
504 SimObjectParam<System *> system; 505 Param<int> cpu_id; 506 507#if FULL_SYSTEM 508 SimObjectParam<AlphaITB *> itb; 509 SimObjectParam<AlphaDTB *> dtb; 510 Param<Tick> profile; 511#else --- 16 unchanged lines hidden (view full) --- 528 "terminate when any thread reaches this inst count"), 529 INIT_PARAM(max_insts_all_threads, 530 "terminate when all threads have reached this inst count"), 531 INIT_PARAM(max_loads_any_thread, 532 "terminate when any thread reaches this load count"), 533 INIT_PARAM(max_loads_all_threads, 534 "terminate when all threads have reached this load count"), 535 INIT_PARAM(progress_interval, "Progress interval"), | 494 SimObjectParam<System *> system; 495 Param<int> cpu_id; 496 497#if FULL_SYSTEM 498 SimObjectParam<AlphaITB *> itb; 499 SimObjectParam<AlphaDTB *> dtb; 500 Param<Tick> profile; 501#else --- 16 unchanged lines hidden (view full) --- 518 "terminate when any thread reaches this inst count"), 519 INIT_PARAM(max_insts_all_threads, 520 "terminate when all threads have reached this inst count"), 521 INIT_PARAM(max_loads_any_thread, 522 "terminate when any thread reaches this load count"), 523 INIT_PARAM(max_loads_all_threads, 524 "terminate when all threads have reached this load count"), 525 INIT_PARAM(progress_interval, "Progress interval"), |
536 INIT_PARAM(mem, "memory"), | |
537 INIT_PARAM(system, "system object"), 538 INIT_PARAM(cpu_id, "processor ID"), 539 540#if FULL_SYSTEM 541 INIT_PARAM(itb, "Instruction TLB"), 542 INIT_PARAM(dtb, "Data TLB"), 543 INIT_PARAM(profile, ""), 544#else --- 21 unchanged lines hidden (view full) --- 566 params->max_loads_all_threads = max_loads_all_threads; 567 params->progress_interval = progress_interval; 568 params->deferRegistration = defer_registration; 569 params->clock = clock; 570 params->functionTrace = function_trace; 571 params->functionTraceStart = function_trace_start; 572 params->width = width; 573 params->simulate_stalls = simulate_stalls; | 526 INIT_PARAM(system, "system object"), 527 INIT_PARAM(cpu_id, "processor ID"), 528 529#if FULL_SYSTEM 530 INIT_PARAM(itb, "Instruction TLB"), 531 INIT_PARAM(dtb, "Data TLB"), 532 INIT_PARAM(profile, ""), 533#else --- 21 unchanged lines hidden (view full) --- 555 params->max_loads_all_threads = max_loads_all_threads; 556 params->progress_interval = progress_interval; 557 params->deferRegistration = defer_registration; 558 params->clock = clock; 559 params->functionTrace = function_trace; 560 params->functionTraceStart = function_trace_start; 561 params->width = width; 562 params->simulate_stalls = simulate_stalls; |
574 params->mem = mem; | |
575 params->system = system; 576 params->cpu_id = cpu_id; 577 578#if FULL_SYSTEM 579 params->itb = itb; 580 params->dtb = dtb; 581 params->profile = profile; 582#else 583 params->process = workload; 584#endif 585 586 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 587 return cpu; 588} 589 590REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU) 591 | 563 params->system = system; 564 params->cpu_id = cpu_id; 565 566#if FULL_SYSTEM 567 params->itb = itb; 568 params->dtb = dtb; 569 params->profile = profile; 570#else 571 params->process = workload; 572#endif 573 574 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 575 return cpu; 576} 577 578REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU) 579 |