atomic.cc (3145:85467cafadbb) | atomic.cc (3169:65bef767b5de) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 239 unchanged lines hidden (view full) --- 248 _status = Idle; 249} 250 251 252template <class T> 253Fault 254AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 255{ | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 239 unchanged lines hidden (view full) --- 248 _status = Idle; 249} 250 251 252template <class T> 253Fault 254AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 255{ |
256 data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); | 256 // use the CPU's statically allocated read request and packet objects 257 Request *req = data_read_req; 258 Packet *pkt = data_read_pkt; |
257 | 259 |
260 req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 261 |
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258 if (traceData) { 259 traceData->setAddr(addr); 260 } 261 262 // translate to physical address | 262 if (traceData) { 263 traceData->setAddr(addr); 264 } 265 266 // translate to physical address |
263 Fault fault = thread->translateDataReadReq(data_read_req); | 267 Fault fault = thread->translateDataReadReq(req); |
264 265 // Now do the access. 266 if (fault == NoFault) { | 268 269 // Now do the access. 270 if (fault == NoFault) { |
267 data_read_pkt->reinitFromRequest(); | 271 pkt->reinitFromRequest(); |
268 | 272 |
269 dcache_latency = dcachePort.sendAtomic(data_read_pkt); | 273 dcache_latency = dcachePort.sendAtomic(pkt); |
270 dcache_access = true; 271 | 274 dcache_access = true; 275 |
272 assert(data_read_pkt->result == Packet::Success); 273 data = data_read_pkt->get<T>(); 274 | 276 assert(pkt->result == Packet::Success); 277 data = pkt->get |
275 } 276 277 // This will need a new way to tell if it has a dcache attached. | 278 } 279 280 // This will need a new way to tell if it has a dcache attached. |
278 if (data_read_req->getFlags() & UNCACHEABLE) | 281 if (req->getFlags() & UNCACHEABLE) |
279 recordEvent("Uncached Read"); 280 281 return fault; 282} 283 284#ifndef DOXYGEN_SHOULD_SKIP_THIS 285 286template --- 36 unchanged lines hidden (view full) --- 323 return read(addr, (uint32_t&)data, flags); 324} 325 326 327template <class T> 328Fault 329AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 330{ | 282 recordEvent("Uncached Read"); 283 284 return fault; 285} 286 287#ifndef DOXYGEN_SHOULD_SKIP_THIS 288 289template --- 36 unchanged lines hidden (view full) --- 326 return read(addr, (uint32_t&)data, flags); 327} 328 329 330template <class T> 331Fault 332AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 333{ |
331 data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); | 334 // use the CPU's statically allocated write request and packet objects 335 Request *req = data_write_req; 336 Packet *pkt = data_write_pkt; |
332 | 337 |
338 req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 339 |
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333 if (traceData) { 334 traceData->setAddr(addr); 335 } 336 337 // translate to physical address | 340 if (traceData) { 341 traceData->setAddr(addr); 342 } 343 344 // translate to physical address |
338 Fault fault = thread->translateDataWriteReq(data_write_req); | 345 Fault fault = thread->translateDataWriteReq(req); |
339 340 // Now do the access. 341 if (fault == NoFault) { 342 data = htog(data); | 346 347 // Now do the access. 348 if (fault == NoFault) { 349 data = htog(data); |
343 data_write_pkt->reinitFromRequest(); 344 data_write_pkt->dataStatic(&data); | 350 pkt->reinitFromRequest(); 351 pkt->dataStatic(&data); |
345 | 352 |
346 dcache_latency = dcachePort.sendAtomic(data_write_pkt); | 353 dcache_latency = dcachePort.sendAtomic(pkt); |
347 dcache_access = true; 348 | 354 dcache_access = true; 355 |
349 assert(data_write_pkt->result == Packet::Success); | 356 assert(pkt->result == Packet::Success); |
350 | 357 |
351 if (res && data_write_req->getFlags() & LOCKED) { 352 *res = data_write_req->getScResult(); | 358 if (res && req->getFlags() & LOCKED) { 359 *res = req->getScResult(); |
353 } 354 } 355 356 // This will need a new way to tell if it's hooked up to a cache or not. | 360 } 361 } 362 363 // This will need a new way to tell if it's hooked up to a cache or not. |
357 if (data_write_req->getFlags() & UNCACHEABLE) | 364 if (req->getFlags() & UNCACHEABLE) |
358 recordEvent("Uncached Write"); 359 360 // If the write needs to have a fault on the access, consider calling 361 // changeStatus() and changing it to "bad addr write" or something. 362 return fault; 363} 364 365 --- 191 unchanged lines hidden --- | 365 recordEvent("Uncached Write"); 366 367 // If the write needs to have a fault on the access, consider calling 368 // changeStatus() and changing it to "bad addr write" or something. 369 return fault; 370} 371 372 --- 191 unchanged lines hidden --- |