atomic.cc (2827:45c3bdb0ffd4) atomic.cc (2856:89691405ec9c)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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50}
51
52const char *
53AtomicSimpleCPU::TickEvent::description()
54{
55 return "AtomicSimpleCPU tick event";
56}
57
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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50}
51
52const char *
53AtomicSimpleCPU::TickEvent::description()
54{
55 return "AtomicSimpleCPU tick event";
56}
57
58Port *
59AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
60{
61 if (if_name == "dcache_port")
62 return &dcachePort;
63 else if (if_name == "icache_port")
64 return &icachePort;
65 else
66 panic("No Such Port\n");
67}
58
59void
60AtomicSimpleCPU::init()
61{
62 //Create Memory Ports (conect them up)
68
69void
70AtomicSimpleCPU::init()
71{
72 //Create Memory Ports (conect them up)
63 Port *mem_dport = mem->getPort("");
64 dcachePort.setPeer(mem_dport);
65 mem_dport->setPeer(&dcachePort);
73// Port *mem_dport = mem->getPort("");
74// dcachePort.setPeer(mem_dport);
75// mem_dport->setPeer(&dcachePort);
66
76
67 Port *mem_iport = mem->getPort("");
68 icachePort.setPeer(mem_iport);
69 mem_iport->setPeer(&icachePort);
77// Port *mem_iport = mem->getPort("");
78// icachePort.setPeer(mem_iport);
79// mem_iport->setPeer(&icachePort);
70
71 BaseCPU::init();
72#if FULL_SYSTEM
73 for (int i = 0; i < threadContexts.size(); ++i) {
74 ThreadContext *tc = threadContexts[i];
75
76 // initialize CPU, including PC
77 TheISA::initCPU(tc, tc->readCpuId());

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81 BaseCPU::init();
82#if FULL_SYSTEM
83 for (int i = 0; i < threadContexts.size(); ++i) {
84 ThreadContext *tc = threadContexts[i];
85
86 // initialize CPU, including PC
87 TheISA::initCPU(tc, tc->readCpuId());

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