atomic.cc (2798:751e9170247e) atomic.cc (2803:0459f5ec8bf8)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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140
141AtomicSimpleCPU::~AtomicSimpleCPU()
142{
143}
144
145void
146AtomicSimpleCPU::serialize(ostream &os)
147{
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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140
141AtomicSimpleCPU::~AtomicSimpleCPU()
142{
143}
144
145void
146AtomicSimpleCPU::serialize(ostream &os)
147{
148 SERIALIZE_ENUM(_status);
149 BaseSimpleCPU::serialize(os);
148 BaseSimpleCPU::serialize(os);
149 SERIALIZE_ENUM(_status);
150 nameOut(os, csprintf("%s.tickEvent", name()));
151 tickEvent.serialize(os);
152}
153
154void
155AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
156{
150 nameOut(os, csprintf("%s.tickEvent", name()));
151 tickEvent.serialize(os);
152}
153
154void
155AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
156{
157 UNSERIALIZE_ENUM(_status);
158 BaseSimpleCPU::unserialize(cp, section);
157 BaseSimpleCPU::unserialize(cp, section);
158 UNSERIALIZE_ENUM(_status);
159 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
160}
161
162void
159 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
160}
161
162void
163AtomicSimpleCPU::switchOut()
163AtomicSimpleCPU::switchOut(Sampler *s)
164{
164{
165 assert(status() == Running || status() == Idle);
166 _status = SwitchedOut;
165 sampler = s;
166 if (status() == Running) {
167 _status = SwitchedOut;
167
168
168 tickEvent.squash();
169 tickEvent.squash();
170 }
171 sampler->signalSwitched();
169}
170
171
172void
173AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
174{
175 BaseCPU::takeOverFrom(oldCPU);
176

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402 // into the CPU object's inst field.
403
404 dcache_access = false; // assume no dcache access
405 preExecute();
406 fault = curStaticInst->execute(this, traceData);
407 postExecute();
408
409 if (simulate_stalls) {
172}
173
174
175void
176AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
177{
178 BaseCPU::takeOverFrom(oldCPU);
179

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405 // into the CPU object's inst field.
406
407 dcache_access = false; // assume no dcache access
408 preExecute();
409 fault = curStaticInst->execute(this, traceData);
410 postExecute();
411
412 if (simulate_stalls) {
410 // This calculation assumes that the icache and dcache
411 // access latencies are always a multiple of the CPU's
412 // cycle time. If not, the next tick event may get
413 // scheduled at a non-integer multiple of the CPU
414 // cycle time.
415 Tick icache_stall = icache_latency - cycles(1);
416 Tick dcache_stall =
417 dcache_access ? dcache_latency - cycles(1) : 0;
413 Tick icache_stall = icache_latency - cycles(1);
414 Tick dcache_stall =
415 dcache_access ? dcache_latency - cycles(1) : 0;
418 latency += icache_stall + dcache_stall;
416 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
417 if (cycles(stall_cycles) < (icache_stall + dcache_stall))
418 latency += cycles(stall_cycles+1);
419 else
420 latency += cycles(stall_cycles);
419 }
420
421 }
422
423 advancePC(fault);
424 }
425
426 if (_status != Idle)

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422
423 }
424
425 advancePC(fault);
426 }
427
428 if (_status != Idle)

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