atomic.cc (2680:246e7104f744) atomic.cc (2683:d6b72bb2ed97)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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191 }
192}
193
194
195void
196AtomicSimpleCPU::activateContext(int thread_num, int delay)
197{
198 assert(thread_num == 0);
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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191 }
192}
193
194
195void
196AtomicSimpleCPU::activateContext(int thread_num, int delay)
197{
198 assert(thread_num == 0);
199 assert(cpuXC);
199 assert(thread);
200
201 assert(_status == Idle);
202 assert(!tickEvent.scheduled());
203
204 notIdleFraction++;
205 tickEvent.schedule(curTick + cycles(delay));
206 _status = Running;
207}
208
209
210void
211AtomicSimpleCPU::suspendContext(int thread_num)
212{
213 assert(thread_num == 0);
200
201 assert(_status == Idle);
202 assert(!tickEvent.scheduled());
203
204 notIdleFraction++;
205 tickEvent.schedule(curTick + cycles(delay));
206 _status = Running;
207}
208
209
210void
211AtomicSimpleCPU::suspendContext(int thread_num)
212{
213 assert(thread_num == 0);
214 assert(cpuXC);
214 assert(thread);
215
216 assert(_status == Running);
217
218 // tick event may not be scheduled if this gets called from inside
219 // an instruction's execution, e.g. "quiesce"
220 if (tickEvent.scheduled())
221 tickEvent.deschedule();
222
223 notIdleFraction--;
224 _status = Idle;
225}
226
227
228template <class T>
229Fault
230AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
231{
215
216 assert(_status == Running);
217
218 // tick event may not be scheduled if this gets called from inside
219 // an instruction's execution, e.g. "quiesce"
220 if (tickEvent.scheduled())
221 tickEvent.deschedule();
222
223 notIdleFraction--;
224 _status = Idle;
225}
226
227
228template <class T>
229Fault
230AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
231{
232 data_read_req->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC());
232 data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
233
234 if (traceData) {
235 traceData->setAddr(addr);
236 }
237
238 // translate to physical address
233
234 if (traceData) {
235 traceData->setAddr(addr);
236 }
237
238 // translate to physical address
239 Fault fault = cpuXC->translateDataReadReq(data_read_req);
239 Fault fault = thread->translateDataReadReq(data_read_req);
240
241 // Now do the access.
242 if (fault == NoFault) {
243 data_read_pkt->reinitFromRequest();
244
245 dcache_latency = dcachePort.sendAtomic(data_read_pkt);
246 dcache_access = true;
247

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299 return read(addr, (uint32_t&)data, flags);
300}
301
302
303template <class T>
304Fault
305AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
306{
240
241 // Now do the access.
242 if (fault == NoFault) {
243 data_read_pkt->reinitFromRequest();
244
245 dcache_latency = dcachePort.sendAtomic(data_read_pkt);
246 dcache_access = true;
247

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299 return read(addr, (uint32_t&)data, flags);
300}
301
302
303template <class T>
304Fault
305AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
306{
307 data_write_req->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC());
307 data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
308
309 if (traceData) {
310 traceData->setAddr(addr);
311 }
312
313 // translate to physical address
308
309 if (traceData) {
310 traceData->setAddr(addr);
311 }
312
313 // translate to physical address
314 Fault fault = cpuXC->translateDataWriteReq(data_write_req);
314 Fault fault = thread->translateDataWriteReq(data_write_req);
315
316 // Now do the access.
317 if (fault == NoFault) {
318 data = htog(data);
319 data_write_pkt->reinitFromRequest();
320 data_write_pkt->dataStatic(&data);
321
322 dcache_latency = dcachePort.sendAtomic(data_write_pkt);

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316 // Now do the access.
317 if (fault == NoFault) {
318 data = htog(data);
319 data_write_pkt->reinitFromRequest();
320 data_write_pkt->dataStatic(&data);
321
322 dcache_latency = dcachePort.sendAtomic(data_write_pkt);

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