atomic.cc (2665:a124942bacb8) atomic.cc (2680:246e7104f744)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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65 mem_dport->setPeer(&dcachePort);
66
67 Port *mem_iport = mem->getPort("");
68 icachePort.setPeer(mem_iport);
69 mem_iport->setPeer(&icachePort);
70
71 BaseCPU::init();
72#if FULL_SYSTEM
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 56 unchanged lines hidden (view full) ---

65 mem_dport->setPeer(&dcachePort);
66
67 Port *mem_iport = mem->getPort("");
68 icachePort.setPeer(mem_iport);
69 mem_iport->setPeer(&icachePort);
70
71 BaseCPU::init();
72#if FULL_SYSTEM
73 for (int i = 0; i < execContexts.size(); ++i) {
74 ExecContext *xc = execContexts[i];
73 for (int i = 0; i < threadContexts.size(); ++i) {
74 ThreadContext *tc = threadContexts[i];
75
76 // initialize CPU, including PC
75
76 // initialize CPU, including PC
77 TheISA::initCPU(xc, xc->readCpuId());
77 TheISA::initCPU(tc, tc->readCpuId());
78 }
79#endif
80}
81
82bool
83AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
84{
85 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");

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174
175void
176AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
177{
178 BaseCPU::takeOverFrom(oldCPU);
179
180 assert(!tickEvent.scheduled());
181
78 }
79#endif
80}
81
82bool
83AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
84{
85 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");

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174
175void
176AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
177{
178 BaseCPU::takeOverFrom(oldCPU);
179
180 assert(!tickEvent.scheduled());
181
182 // if any of this CPU's ExecContexts are active, mark the CPU as
182 // if any of this CPU's ThreadContexts are active, mark the CPU as
183 // running and schedule its tick event.
183 // running and schedule its tick event.
184 for (int i = 0; i < execContexts.size(); ++i) {
185 ExecContext *xc = execContexts[i];
186 if (xc->status() == ExecContext::Active && _status != Running) {
184 for (int i = 0; i < threadContexts.size(); ++i) {
185 ThreadContext *tc = threadContexts[i];
186 if (tc->status() == ThreadContext::Active && _status != Running) {
187 _status = Running;
188 tickEvent.schedule(curTick);
189 break;
190 }
191 }
192}
193
194

--- 336 unchanged lines hidden --- 		187 _status = Running;
188 tickEvent.schedule(curTick);
189 break;
190 }
191 }
192}
193
194

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