atomic.cc (2662:f24ae2d09e27) | atomic.cc (2663:c82193ae8467) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 106 unchanged lines hidden (view full) --- 115 116AtomicSimpleCPU::AtomicSimpleCPU(Params *p) 117 : BaseSimpleCPU(p), tickEvent(this), 118 width(p->width), simulate_stalls(p->simulate_stalls), 119 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this) 120{ 121 _status = Idle; 122 | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 106 unchanged lines hidden (view full) --- 115 116AtomicSimpleCPU::AtomicSimpleCPU(Params *p) 117 : BaseSimpleCPU(p), tickEvent(this), 118 width(p->width), simulate_stalls(p->simulate_stalls), 119 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this) 120{ 121 _status = Idle; 122 |
123 ifetch_req = new Request(true); 124 ifetch_req->setAsid(0); 125 // @todo fix me and get the real cpu iD!!! 126 ifetch_req->setCpuNum(0); 127 ifetch_req->setSize(sizeof(MachInst)); | 123 // @todo fix me and get the real cpu id & thread number!!! 124 ifetch_req = new Request(); |
128 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 129 ifetch_pkt->dataStatic(&inst); 130 | 125 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 126 ifetch_pkt->dataStatic(&inst); 127 |
131 data_read_req = new Request(true); 132 // @todo fix me and get the real cpu iD!!! 133 data_read_req->setCpuNum(0); 134 data_read_req->setAsid(0); | 128 data_read_req = new Request(); |
135 data_read_pkt = new Packet(data_read_req, Packet::ReadReq, 136 Packet::Broadcast); 137 data_read_pkt->dataStatic(&dataReg); 138 | 129 data_read_pkt = new Packet(data_read_req, Packet::ReadReq, 130 Packet::Broadcast); 131 data_read_pkt->dataStatic(&dataReg); 132 |
139 data_write_req = new Request(true); 140 // @todo fix me and get the real cpu iD!!! 141 data_write_req->setCpuNum(0); 142 data_write_req->setAsid(0); | 133 data_write_req = new Request(); |
143 data_write_pkt = new Packet(data_write_req, Packet::WriteReq, 144 Packet::Broadcast); 145} 146 147 148AtomicSimpleCPU::~AtomicSimpleCPU() 149{ 150} --- 80 unchanged lines hidden (view full) --- 231 _status = Idle; 232} 233 234 235template <class T> 236Fault 237AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 238{ | 134 data_write_pkt = new Packet(data_write_req, Packet::WriteReq, 135 Packet::Broadcast); 136} 137 138 139AtomicSimpleCPU::~AtomicSimpleCPU() 140{ 141} --- 80 unchanged lines hidden (view full) --- 222 _status = Idle; 223} 224 225 226template <class T> 227Fault 228AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 229{ |
239 data_read_req->setVaddr(addr); 240 data_read_req->setSize(sizeof(T)); 241 data_read_req->setFlags(flags); 242 data_read_req->setTime(curTick); | 230 data_read_req->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC()); |
243 244 if (traceData) { 245 traceData->setAddr(addr); 246 } 247 248 // translate to physical address 249 Fault fault = cpuXC->translateDataReadReq(data_read_req); 250 --- 58 unchanged lines hidden (view full) --- 309 return read(addr, (uint32_t&)data, flags); 310} 311 312 313template <class T> 314Fault 315AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 316{ | 231 232 if (traceData) { 233 traceData->setAddr(addr); 234 } 235 236 // translate to physical address 237 Fault fault = cpuXC->translateDataReadReq(data_read_req); 238 --- 58 unchanged lines hidden (view full) --- 297 return read(addr, (uint32_t&)data, flags); 298} 299 300 301template <class T> 302Fault 303AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 304{ |
317 data_write_req->setVaddr(addr); 318 data_write_req->setTime(curTick); 319 data_write_req->setSize(sizeof(T)); 320 data_write_req->setFlags(flags); | 305 data_write_req->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC()); |
321 322 if (traceData) { 323 traceData->setAddr(addr); 324 } 325 326 // translate to physical address 327 Fault fault = cpuXC->translateDataWriteReq(data_write_req); 328 --- 74 unchanged lines hidden (view full) --- 403{ 404 Tick latency = cycles(1); // instruction takes one cycle by default 405 406 for (int i = 0; i < width; ++i) { 407 numCycles++; 408 409 checkForInterrupts(); 410 | 306 307 if (traceData) { 308 traceData->setAddr(addr); 309 } 310 311 // translate to physical address 312 Fault fault = cpuXC->translateDataWriteReq(data_write_req); 313 --- 74 unchanged lines hidden (view full) --- 388{ 389 Tick latency = cycles(1); // instruction takes one cycle by default 390 391 for (int i = 0; i < width; ++i) { 392 numCycles++; 393 394 checkForInterrupts(); 395 |
411 ifetch_req->resetMin(); | |
412 Fault fault = setupFetchRequest(ifetch_req); 413 414 if (fault == NoFault) { 415 ifetch_pkt->reinitFromRequest(); 416 417 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt); 418 // ifetch_req is initialized to read the instruction directly 419 // into the CPU object's inst field. --- 125 unchanged lines hidden --- | 396 Fault fault = setupFetchRequest(ifetch_req); 397 398 if (fault == NoFault) { 399 ifetch_pkt->reinitFromRequest(); 400 401 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt); 402 // ifetch_req is initialized to read the instruction directly 403 // into the CPU object's inst field. --- 125 unchanged lines hidden --- |